50.12.44 SDMMC Additional Present State Register
The reset value depends on the instance
of the SDMMC:
Instance | Reset Value |
---|---|
SDMMC0 | 0x0000000F |
SDMMC1 | 0x00000000 |
Name: | SDMMC_APSR |
Offset: | 0x200 |
Reset: | – |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
HDATLL[3:0] | |||||||||
Access | R | R | R | R | |||||
Reset | – | – | – | – |
Bits 3:0 – HDATLL[3:0] DAT[7:4] High Line Level
This status is used to check the DAT[7:4] line level to recover from errors, and for debugging.