46.10.61 TWI Control Register (FIFO_ENABLED)

If FIFO is enabled (FLEX_US_CR.FIFOEN=1), see TWI Multiple Data Access for details.

This register can only be written if the WPCREN bit is cleared in the TWI Write Protection Mode register.

Name: FLEX_TWI_CR (FIFO_ENABLED)
Offset: 0x600
Reset: 
Property: Write-only

Bit 3130292827262524 
   FIFODISFIFOEN TXFLCLRRXFCLRTXFCLR 
Access WWWWW 
Reset  
Bit 2322212019181716 
       ACMDISACMEN 
Access WW 
Reset  
Bit 15141312111098 
 CLEARPECRQPECDISPECENSMBDISSMBENHSDISHSEN 
Access WWWWWWWW 
Reset  
Bit 76543210 
 SWRSTQUICKSVDISSVENMSDISMSENSTOPSTART 
Access WWWWWWWW 
Reset  

Bit 29 – FIFODIS FIFO Disable

ValueDescription
0

No effect.

1

Disable the Transmit and Receive FIFOs.

Bit 28 – FIFOEN FIFO Enable

ValueDescription
0

No effect.

1

Enable the Transmit and Receive FIFOs.

Bit 26 – TXFLCLR Transmit FIFO Lock CLEAR

ValueDescription
0

No effect.

1

Clears the Transmit FIFO Lock.

Bit 25 – RXFCLR Receive FIFO Clear

ValueDescription
0

No effect.

1

Empties the Receive FIFO.

Bit 24 – TXFCLR Transmit FIFO Clear

ValueDescription
0

No effect.

1

Empties the Transmit FIFO.

Bit 17 – ACMDIS Alternative Command Mode Disable

ValueDescription
0

No effect.

1

Alternative Command mode disabled.

Bit 16 – ACMEN Alternative Command Mode Enable

ValueDescription
0

No effect.

1

Alternative Command mode enabled.

Bit 15 – CLEAR Bus CLEAR Command

ValueDescription
0

No effect.

1

If Host mode is enabled, send a bus clear command.

Bit 14 – PECRQ PEC Request

ValueDescription
0

No effect.

1

A PEC check or transmission is requested.

Bit 13 – PECDIS Packet Error Checking Disable

ValueDescription
0

No effect.

1

SMBus PEC (CRC) generation and check disabled.

Bit 12 – PECEN Packet Error Checking Enable

ValueDescription
0

No effect.

1

SMBus PEC (CRC) generation and check enabled.

Bit 11 – SMBDIS SMBus Mode Disabled

ValueDescription
0

No effect.

1

SMBus mode disabled.

Bit 10 – SMBEN SMBus Mode Enabled

ValueDescription
0

No effect.

1

If SMBDIS = 0, SMBus mode enabled.

Bit 9 – HSDIS TWI High-Speed Mode Disabled

ValueDescription
0

No effect.

1

High-speed mode disabled.

Bit 8 – HSEN TWI High-Speed Mode Enabled

ValueDescription
0

No effect.

1

High-speed mode enabled.

Bit 7 – SWRST Software Reset

ValueDescription
0

No effect.

1

Equivalent to a system reset.

Bit 6 – QUICK SMBus Quick Command

ValueDescription
0

No effect.

1

If Host mode is enabled, a SMBus Quick Command is sent.

Bit 5 – SVDIS TWI Client Mode Disabled

ValueDescription
0

No effect.

1

Client mode is disabled. The shifter and holding characters (if it contains data) are transmitted in the case of a read operation. In a write operation, the character being transferred must be completely received before disabling.

Bit 4 – SVEN TWI Client Mode Enabled

Switching from Host to Client mode is only permitted when TXCOMP = 1.
ValueDescription
0

No effect.

1

Enables Client mode (SVDIS must be written to 0).

Bit 3 – MSDIS TWI Host Mode Disabled

ValueDescription
0

No effect.

1

Host mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in the case of a write operation. In a read operation, the character being transferred must be completely received before disabling.

Bit 2 – MSEN TWI Host Mode Enabled

Switching from Client to Host mode is only permitted when TXCOMP = 1.
ValueDescription
0

No effect.

1

Enables Host mode (MSDIS must be written to 0).

Bit 1 – STOP Send a STOP Condition

ValueDescription
0

No effect.

1

STOP condition is sent just after completing the current byte transmission in Host Read mode.

– In single data byte host read, both START and STOP must be set.

– In multiple data bytes host read, the STOP must be set after the last data received but one.

– In Host Read mode, if a NACK bit is received, the STOP is automatically performed.

– In host data write operation, a STOP condition will be sent after the transmission of the current data is finished.

Bit 0 – START Send a START Condition

This action is necessary when the TWI peripheral needs to read data from a client. When configured in Host mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding register (FLEX_TWI_THR).

ValueDescription
0

No effect.

1

A frame beginning with a START bit is transmitted according to the features defined in the TWI Host Mode register (FLEX_TWI_MMR).