47.5.6 Asynchronous and Partial Wake-Up

Asynchronous and partial wake-up is a means of data pre-processing that qualifies an incoming event, thus allowing the UART to decide whether or not to wake up the system. This operating mode is used primarily when the system is in ULP1 mode (refer to section “Power Management Controller (PMC)”) but can also be enabled when the system is fully running.

No access must be performed in the UART between the enable of Asynchronous and Partial Wake-up and the wake-up performed by the UART.

If the system is in ULP1 mode and Asynchronous and Partial Wake-up is enabled, the maximum baud rate that can be achieved equals 19200.

If the system is running or in Sleep mode, the maximum baud rate that can be achieved equals 115200 or higher. This limit is bounded by the peripheral clock frequency divided by 16.

The UART_RHR must be read before enabling Asynchronous and Partial Wake-up.

When Asynchronous and Partial Wake-up is enabled for the UART (refer to section “Power Management Controller (PMC)”), the PMC decodes a clock request from the UART. The request is generated as soon as there is a falling edge on the URXD line as this may indicate the beginning of a start bit. If the system is in ULP1 mode (processor and peripheral clocks switched off), the PMC restarts the fast RC oscillator and provides the clock only to the UART.

As soon as the clock is provided by the PMC, the UART processes the received frame and compares the received character with VAL1 and VAL2 in UART_CMPR (UART Comparison Register).

The UART instructs the PMC to disable the clock if the received character value does not meet the conditions defined by VAL1 and VAL2 fields in UART_CMPR (see Asynchronous Event Generating Only Partial Wake-up).

If the received character value meets the conditions, the UART instructs the PMC to exit the full system from ULP1 mode (see Asynchronous Wake-up Use Case Examples).

The VAL1 and VAL2 fields can be programmed to provide different comparison methods and thus matching conditions.

• If VAL1 equals VAL2, then the comparison is performed on a single value and the wake-up is triggered if the received character equals VAL1.
• If VAL1 is strictly lower than VAL2, then any value between VAL1 and VAL2 wakes up the system.
• If VAL1 is strictly higher than VAL2, then the wake-up is triggered if the received character equals VAL1 or VAL2.
• If VAL1 = 0 and VAL2 = 255, the wake-up is triggered as soon as a character is received.

The matching condition can be configured to include the parity bit (CMPPAR in UART_CMPR). Thus, if the received data matches the comparison condition defined by VAL1 and VAL2 but a parity error is encountered, the matching condition is canceled and the UART instructs the PMC to disable the clock (see Asynchronous Event Generating Only Partial Wake-up).

If the processor and peripherals are running, the UART can be configured in Asynchronous and Partial Wake-up mode by enabling the PMC_SLPWK_ER (refer to "Power Management Controller (PMC)"). When activity is detected on the receive line, the UART requests the clock from the PMC and the comparison is performed. If there is a comparison match, the UART continues to request the clock. If there is no match, the clock is switched off for the UART only, until a new activity is detected.

The CMPMODE configuration has no effect when Asynchronous and Partial Wake-up mode is enabled for the UART (refer to PMC_SLPWK_ER in "Power Management Controller (PMC)").

When the system is kept in active/running mode and the UART enters Asynchronous and Partial Wake-up mode, the flag CMP must be programmed as the unique source of the UART interrupt.

When the system exits ULP1 mode as the result of a matching condition, the RXRDY flag is used to determine if the UART is the source of exit.