32.22.7 PMC UTMI Clock Configuration Register
Name: | CKGR_UCKR |
Offset: | 0x001C |
Reset: | 0x10200000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
BIASCOUNT[3:0] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 1 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
UPLLCOUNT[3:0] | UPLLEN | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 1 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Access | |||||||||
Reset |
Bits 31:28 – BIASCOUNT[3:0] UTMI BIAS Start-up Time
Specifies the number of slow clock cycles for the UTMI BIAS start-up time.
Bits 23:20 – UPLLCOUNT[3:0] UTMI PLL Start-up Time
Specifies the number of slow clock cycles multiplied by 8 for the UTMI PLL start-up time.
Bit 16 – UPLLEN UTMI PLL Enable
When UPLLEN is set, the LOCKU flag is set once the UTMI PLL start-up time is achieved.
Value | Description |
---|---|
0 | The UTMI PLL is disabled. |
1 | The UTMI PLL is enabled. |