35.7.12 MPDDRC I/O Calibration Register
| Name: | MPDDRC_IO_CALIBR |
| Offset: | 0x34 |
| Reset: | 0x00870000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CALCODEN[3:0] | CALCODEP[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TZQIO[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN_CALIB | RDIV[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 23:20 – CALCODEN[3:0] Number of N-type Transistors
Gives the number of N-type transistors to perform the calibration.
Bits 19:16 – CALCODEP[3:0] Number of P-type Transistors
Gives the number of P-type transistors to perform the calibration.
Bits 14:8 – TZQIO[6:0] IO Calibration
Defines the delay between the start up of the amplifier and the beginning of the calibration, in number of DDRCK clock cycles. The value of this field must be set to 600 ns. The number of cycles is between 0 and 127.
- TZQIO = (DDRCK × (600 × 10-9)) + 1
where the DDRCK frequency is in Hz.
For example, for a frequency of 176 MHz, the value of the TZQIO field is configured (176 × 106) × (600 × 10-9) + 1.
Bit 4 – EN_CALIB Enable Calibration
Enables calibration for the LPDDR1 and DDR2 devices. When the calibration is enabled, it is recommended to define the COUNT_CAL field (see “COUNT_CAL: LPDDR2 LPDDR3 and DDR3 Calibration Timer Count”).
This 16-bit field is loaded into a timer which generates the calibration pulse. Each time the calibration pulse is generated, a calibration sequence is initiated.
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE_CALIBRATION | Calibration is disabled. |
| 1 | ENABLE_CALIBRATION | Calibration is enabled. |
Bits 2:0 – RDIV[2:0] Resistor Divider, Output Driver Impedance
RDIV is used with the external precision resistor RZQ to define the output driver impedance. The value of RZQ is either 24K ohms (LPDDR2/LPDDR3 device) or 23K ohms (DDR3L device) or 22K ohms (DDR3 device) or 21K ohms (DDR2/LPDDR1 device).
| Value | Name | Description |
|---|---|---|
| 0 | Reserved |
Reserved |
| 2 | RZQ_40_RZQ_38_RZQ_37_RZQ_35 |
LPDDR2 serial impedance line = 40 ohms, LPDDR3 serial impedance line = 38 ohms, DDR3 serial impedance line = 37 ohms, DDR2/LPDDR1 serial impedance line = 35 ohms |
| 3 | RZQ_48_RZQ_46_RZQ_44_RZQ_43 |
LPDDR2 serial impedance line = 48 ohms, LPDDR3 serial impedance line = 46 ohms, DDR3 serial impedance line = 44 ohms, DDR2/LPDDR1 serial impedance line = 43 ohms |
| 4 | RZQ_60_RZQ_57_RZQ_55_RZQ_52 |
LPDDR2 serial impedance line = 60 ohms, LPDDR3 serial impedance line = 57 ohms, DDR3 serial impedance line = 55 ohms, DDR2/LPDDR1 serial impedance line = 52 ohms |
| 6 | RZQ_80_RZQ_77_RZQ_73_RZQ_70 |
LPDDR2 serial impedance line = 80 ohms, LPDDR3 serial impedance line = 77 ohms, DDR3 serial impedance line = 73 ohms, DDR2/LPDDR1 serial impedance line = 70 ohms |
| 7 | RZQ_120_RZQ_115_RZQ_110_RZQ_105 |
LPDDR2 serial impedance line = 120 ohms, LPDDR3 serial impedance line = 115 ohms, DDR3 serial impedance line = 110 ohms, DDR2/LPDDR1 serial impedance line = 105 ohms |