55.7.32 PWM Stepper Motor Mode Register

This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.

Name: PWM_SMMR
Offset: 0xB0
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       DOWN1DOWN0 
Access R/WR/W 
Reset 00 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       GCEN1GCEN0 
Access R/WR/W 
Reset 00 

Bits 16, 17 – DOWNx Down Count

ValueDescription
0

Up counter.
1

Down counter.

Bits 0, 1 – GCENx Gray Count Enable

ValueDescription
0

Disable Gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1]
1

Enable Gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1].