19.3.13 HRAMC L2CC Register

This register is used to configure the L2 cache to be used as an internal SRAM.

Name: SFR_L2CC_HRAMC
Offset: 0x58
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
        SRAM_SEL 
Access R/W 
Reset 0 

Bit 0 – SRAM_SEL SRAM Selector

ValueDescription
0 Selects SRAM.
1 Selects L2CC.