47.6.2 UART Mode Register
Name: | UART_MR |
Offset: | 0x04 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CHMODE[1:0] | BRSRCCK | PAR[2:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
FILTER | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bits 15:14 – CHMODE[1:0] Channel Mode
Value | Name | Description |
---|---|---|
0 | NORMAL | Normal mode |
1 | AUTOMATIC | Automatic echo |
2 | LOCAL_LOOPBACK | Local loopback |
3 | REMOTE_LOOPBACK | Remote loopback |
Bit 12 – BRSRCCK Baud Rate Source Clock
0 (PERIPH_CLK): The baud rate is driven by the peripheral clock
1 (GCLK): The baud rate is driven by a PMC-programmable clock GCLK (refer to section "Power Management Controller (PMC)").
Bits 11:9 – PAR[2:0] Parity Type
Value | Name | Description |
---|---|---|
0 | EVEN | Even parity |
1 | ODD | Odd parity |
2 | SPACE | Space: parity forced to 0 |
3 | MARK | Mark: parity forced to 1 |
4 | NO | No parity |
Bit 4 – FILTER Receiver Digital Filter
0 (DISABLED): UART does not filter the receive line.
1 (ENABLED): UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).