60.5.1 SHA Control Register
| Name: | SHA_CR |
| Offset: | 0x00 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WUIEHV | WUIHV | SWRST | |||||||
| Access | W | W | W | ||||||
| Reset | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FIRST | START | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
Bit 13 – WUIEHV Write User Initial or Expected Hash Values
| Value | Description |
|---|---|
| 0 | SHA_IDATARx accesses are routed to the data registers. |
| 1 | SHA_IDATARx accesses are routed to the internal registers (IR1). |
Bit 12 – WUIHV Write User Initial Hash Values
| Value | Description |
|---|---|
| 0 | SHA_IDATARx accesses are routed to the data registers. |
| 1 | SHA_IDATARx accesses are routed to the internal registers (IR0). |
Bit 8 – SWRST Software Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Resets the SHA. A software-triggered hardware reset of the SHA interface is performed. |
Bit 4 – FIRST First Block of a Message
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Indicates that the next block to process is the first one of a message or the first block of a fragment of a message. |
Bit 0 – START Start Processing
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Starts manual hash algorithm process. |