44.9.6 SSC Transmit Frame Mode Register

This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.

Name: SSC_TFMR
Offset: 0x1C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 FSLEN_EXT[3:0]   FSEDGE 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 2322212019181716 
 FSDENFSOS[2:0]FSLEN[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
     DATNB[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 MSBF DATDEFDATLEN[4:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 31:28 – FSLEN_EXT[3:0] FSLEN Field Extension

Extends FSLEN field. For details, see FSLEN description below.

Bit 24 – FSEDGE Frame Sync Edge Detection

Determines which edge on frame synchronization will generate the interrupt TXSYN (Status Register).

ValueNameDescription
0 POSITIVE Positive Edge Detection
1 NEGATIVE Negative Edge Detection

Bit 23 – FSDEN Frame Sync Data Enable

ValueDescription
0 The TD line is driven with the default value during the Transmit Frame Sync signal.
1 SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.

Bits 22:20 – FSOS[2:0] Transmit Frame Sync Output Selection

ValueNameDescription
0 NONE None, TF pin is an input
1 NEGATIVE Negative Pulse, TF pin is an output
2 POSITIVE Positive Pulse, TF pin is an output
3 LOW Driven Low during data transfer
4 HIGH Driven High during data transfer
5 TOGGLING Toggling at each start of data transfer

Bits 19:16 – FSLEN[3:0] Transmit Frame Sync Length

This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from SSC_TSHR if FSDEN is 1.

This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal.

Pulse length is equal to FSLEN + (FSLEN_EXT × 16) + 1 Transmit Clock period.

Bits 11:8 – DATNB[3:0] Data Number per Frame

This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1).

Bit 7 – MSBF Most Significant Bit First

ValueDescription
0 The lowest significant bit of the data register is shifted out first in the bit stream.
1 The most significant bit of the data register is shifted out first in the bit stream.

Bit 5 – DATDEF Data Default Value

This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1.

When the TD pin is configured in Multi-drive (Open-drain) mode by the PIO controller, a 0 is driven if SSC data output equals 0 and the pin is in high-impedance when SSC data output is 1.

Bits 4:0 – DATLEN[4:0] Data Length

ValueDescription
0 Forbidden value (1-bit data length not supported).
Any other value The bit stream contains DATLEN + 1 data bits.