39.1 GMAC Network Control Register


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					TXLPIEN	FNP	TXPBPF	ENPBPR
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	SRTSM			TXZQPF	TXPF	THALT	TSTART	BP
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	WESTAT	INCSTAT	CLRSTAT	MPE	TXEN	RXEN	LBL
Access	R/W	W	W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0

Bit 19 – TXLPIEN Enable LPI Transmission

When set, LPI (low power idle) is immediately transmitted.

Bit 18 – FNP Flush Next Packet

Flush the next packet from the external receive memory. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the receive memory to system memory.

Value	Description
0	No effect.
1	Flushes the next packet from the receive memory. This will only have an effect if the DMA is not currently writing a packet already stored in the receive memory to system memory.

Bit 17 – TXPBPF Transmit PFC Priority-based Pause Frame

Value	Description
0	No effect.
1	Takes the values stored in the Transmit PFC Pause Register.

Bit 16 – ENPBPR Enable PFC Priority-based Pause Reception

Enables PFC Priority Based Pause Reception capabilities. Setting this bit enables PFC negotiation and recognition of priority-based pause frames.

Bit 15 – SRTSM Store Receive Timestamp to Memory

Value	Description
0	No effect.
1	Causes the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message timestamp point. Note that bit RFCS in register GMAC_NCFGR may not be set to 1 when the timer should be captured.

Bit 12 – TXZQPF Transmit Zero Quantum Pause Frame

Value	Description
0	No effect.
1	Generates a pause frame with zero quantum to be transmitted.

Bit 11 – TXPF Transmit Pause Frame

Value	Description
0	No effect.
1	Generates a pause frame to be transmitted.

Bit 10 – THALT Transmit Halt

Value	Description
0	No effect.
1	Halts transmission as soon as any ongoing frame transmission ends.

Bit 9 – TSTART Start Transmission

Value	Description
0	No effect.
1	Starts transmission.

Bit 8 – BP Back pressure

Value	Description
0	No effect.
1	When the MAC is set in 10M or 100M Half Duplex mode, forces collisions on all received frames.

Bit 7 – WESTAT Write Enable for Statistics Registers

Value	Description
0	Forces the statistics registers to be in read-only mode for normal operation mode.
1	Makes the statistics registers writable for functional test purposes.

Bit 6 – INCSTAT Increment Statistics Registers

Bit 5 – CLRSTAT Clear Statistics Registers

Value	Description
0	No effect.
1	Clears the statistics registers.

Bit 4 – MPE Management Port Enable

Set to one to enable the management port. When zero, forces GMDIO to high impedance state and MDC low.

Value	Description
0	Forces GMDIO to high impedance state and MDC low.
1	Enables the management port.

Bit 3 – TXEN Transmit Enable

Value	Description
0	Stops transmission immediately, the transmit pipeline and control registers will be cleared and the Transmit Queue Pointer register will reset to point to the start of the transmit descriptor list.
1	Enables the GMAC transmitter to send data.

Bit 2 – RXEN Receive Enable

When set, RXEN enables the GMAC to receive data. When reset frame reception stops immediately and the receive pipeline will be cleared. The Receive Queue Pointer Register is unaffected.

Value	Description
0	Stops frame reception immediately and the receive pipeline will be cleared. The Receive Queue Pointer register is unaffected.
1	Enables the GMAC to receive data.

Bit 1 – LBL Loop Back Local

Value	Description
0	Normal operating mode (no loop back).
1	Connects GTX to GRX, GTXEN to GRXDV and forces Full Duplex mode. GRXCK and GTXCK may malfunction as the GMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back.