48.7.7.1 Overview

The SPI includes two FIFOs which can be enabled/disabled using SPI_CR.FIFOEN/FIFODIS. The SPI must be disabled (SPI_CR.SPIDIS) before enabling or disabling the SPI FIFOs.

Writing SPI_CR.FIFOEN to ‘1’ enables a 16-data Transmit FIFO and a 16-data Receive FIFO.

It is possible to write or to read single or multiple data in the same access to SPI_TDR/RDR. Refer to sections Single Data Mode and Multiple Data Mode.