45.7.19 TWIHS Transmit Holding Register (FIFO Enabled)
If FIFO is enabled (FIFOEN bit in TWIHS_CR), refer to 45.6.6.8 Multiple Data Mode for details.
Name: | TWIHS_THR (FIFO_ENABLED) |
Offset: | 0x34 |
Reset: | 0x00000000 |
Property: | Write-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
TXDATA3[7:0] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
TXDATA2[7:0] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
TXDATA1[7:0] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TXDATA0[7:0] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |