55.7.50 PWM Leading-Edge Blanking Register

This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.

Name: PWM_LEBRx
Offset: 0x0430 + (x-1)*0x20 [x=1..2]
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     PWMHRENPWMHFENPWMLRENPWMLFEN 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
  LEBDELAY[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 19 – PWMHREN PWMH Rising Edge Enable

ValueDescription
0

Leading-edge blanking is disabled on PWMHx output rising edge.

1

Leading-edge blanking is enabled on PWMHx output rising edge.

Bit 18 – PWMHFEN PWMH Falling Edge Enable

ValueDescription
0

Leading-edge blanking is disabled on PWMHx output falling edge.

1

Leading-edge blanking is enabled on PWMHx output falling edge.

Bit 17 – PWMLREN PWML Rising Edge Enable

ValueDescription
0

Leading-edge blanking is disabled on PWMLx output rising edge.

1

Leading-edge blanking is enabled on PWMLx output rising edge.

Bit 16 – PWMLFEN PWML Falling Edge Enable

ValueDescription
0

Leading-edge blanking is disabled on PWMLx output falling edge.

1

Leading-edge blanking is enabled on PWMLx output falling edge.

Bits 6:0 – LEBDELAY[6:0] Leading-Edge Blanking Delay for TRGINx

Leading-edge blanking duration for external trigger x input. The delay is calculated according to the following formula:

LEBDELAY = (fperipheral clock × Delay) + 1