18.4.3 Host to Client Access
The following table shows how hosts and clients interconnect. Writing in a register or field not dedicated to a host or a client has no effect.
| HOST | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 (Through Bridge from H64MX) | 1 | 2 | 3 | 4 | 5 | 6 | 7 | ||||||
| CLIENT | Core | XDMAC0 | XDMAC1 | ICM | UHPHS EHCI DMA | UHPHS OHCI DMA | UDPHS DMA | GMAC DMA | CAN0 DMA | CAN1 DMA | |||
| IF0 | IF1 | IF0 | IF1 | ||||||||||
| 0 | Bridge from H32MX to H64MX | – | – | – | – | – | X | X | X | X | X | X | X |
| 1 | H32MX Peripheral Bridge 0 | X | – | X | – | X | – | – | – | – | – | – | – |
| 2 | H32MX Peripheral Bridge 1 | X | – | X | – | X | – | – | – | – | – | – | – |
| 3 | EBI CS0..CS3 | X | X | – | X | – | X | – | – | – | – | – | – |
| NFC Command Register | X | X | – | X | – | – | – | – | – | – | – | – | |
| 4 | NFC SRAM | X | X | – | X | – | – | – | – | – | – | – | – |
| 5 | UDPHS RAM | X | – | – | – | X | – | – | – | – | – | – | – |
| UHP OHCI Reg | X | – | – | – | X | – | – | – | – | – | – | – | |
| UHP EHCI Reg | X | – | – | – | X | – | – | – | – | – | – | – | |
| 6 | Peripheral Touch Controller (PTC) | X | – | – | – | – | – | – | – | – | – | – | – |