58.5.6 AESB Interrupt Status Register
Name: | AESB_ISR |
Offset: | 0x1C |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
URAT[3:0] | URAD | ||||||||
Access | R | R | R | R | R | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DATRDY | |||||||||
Access | R | ||||||||
Reset | 0 |
Bits 15:12 – URAT[3:0] Unspecified Register Access
Only the last Unspecified Register Access Type is available through URAT.
URAT field is reset only by AESB_CR.SWRST.
Value | Name | Description |
---|---|---|
0x0 | IDR_WR_PROCESSING | Input Data register written during the data processing when SMOD = 0x2 mode |
0x1 | ODR_RD_PROCESSING | Output Data register read during the data processing |
0x2 | MR_WR_PROCESSING | Mode register written during the data processing |
0x3 | ODR_RD_SUBKGEN | Output Data register read during the sub-keys generation |
0x4 | MR_WR_SUBKGEN | Mode register written during the sub-keys generation |
0x5 | WOR_RD_ACCESS | Write-only register read access |
Bit 8 – URAD Unspecified Register Access Detection Status
URAD is reset only by AESB_CR.SWRST.
Value | Description |
---|---|
0 | No unspecified register access has been detected since the last SWRST. |
1 | At least one unspecified register access has been detected since the last SWRST. |
Bit 0 – DATRDY Data Ready
DATRDY is cleared when a Manual encryption/decryption occurs (AESB_CR.START) or when a software triggered hardware reset of the AESB interface is performed (AESB_CR.SWRST).
AESB_MR.LOD = 0: In Manual and Auto modes, DATRDY can also be cleared when at least one of the Output Data registers is read.
AESB_MR.LOD = 1: In Manual and Auto modes, DATRDY can also be cleared when at least one of the Input Data registers is written.
Value | Description |
---|---|
0 | Output data not valid. |
1 | Encryption or decryption process is completed. |