29.5.1 Power Management

The PTC Controller is not continuously clocked. The programmer must first enable the PTC Controller peripheral clock in the Power Management Controller (PMC) before using the PTC Controller. However, if the application does not require PTC operations, the PTC Controller clock can be stopped when not needed and restarted when necessary. Configuring the PTC Controller requires the PTC Controller clock to be enabled.

Figure 29-2. PTC Subsystem Clock Sources

The PTC subsystem operates both from a peripheral clock synchronous to the main system bus clock of the system and from an asynchronous clock source directly connected to the embedded 12 MHz RC oscillator. The selected clocks must be enabled in the PMC before they can be used by the PTC. By default, the 12 MHz RC oscillator is enabled at startup of the product.

The various clock sources are as follows:

  • PERIPH_CLK_PTC

This clock source is dedicated to the picoPower processor. It is located in the PMC as Periph_clk[PID]=PCLOCK_LS. This clock is synchronous with the AHB/APB matrix controlling the host interface and the mailbox. The clock frequency is between 12 MHz and 83 MHz. The same clock is used for the Arm interface connected as an APB client via an AHB/APB bridge. It is also used to program the code/data SRAM and to access the mailbox SRAM.

  • RC12MHZ

A different clock is used for the PTC digital controller. This clock can be divided internally in the pPP before being used. There is also a small local prescaler in the PTC digital controller to allow lower clock rates. Thus, the PTC operates from an asynchronous clock source and the operation is independent from the main system clock and its derivative clocks, such as the peripheral bus clock (PERIPH_CLK_PTC).

  • SCLK

For the timers, a 32 kHz clock is used and divided internally down to a 1 kHz clock for counting the timer interrupt.

Figure 29-3. PTC Subsystem Clock Schematic

The RC12HMZ clock is internally divided by 3 in the PTC subsystem, and so a 4 MHz clock is provided to the PTC digital controller. This controller can divide the clock further by 1, 2, 4 or 8 to slow down the PTC clock.

  • ADC_CLK

The prescaled clock PTC_CLK is divided by 4 to supply an ADC_CLK to the PTC analog front end.

The ADC data rate is defined by the controller. The typical value is about 33 kHz to 66 kHz depending on the timing configuration.