18.2 Embedded Characteristics

  • 32-bit or 64-bit Data Bus
  • 64-bit Matrix (H64MX) Providing 12 Hosts and 15 Clients
  • 32-bit Matrix (H32MX) Providing 8 Hosts and 6 Clients
  • One Address Decoder for Each Host
  • Support for Long Bursts of Length 32, 64, 128 and Up to the Limit of 256-bit Burst Beats of Words
  • Enhanced Programmable Mixed Arbitration for Each Client:
    • Round-robin
    • Fixed priority
    • Latency quality of service
  • Programmable Default Host for Each Client:
    • No default host
    • Last accessed default host
    • Fixed default host
  • Deterministic Maximum Access Latency for Hosts
  • Zero or One Cycle Arbitration Latency for the First Access of a Burst
  • Bus Lock Forwarding to Clients
  • One Special Function Register for Each Client (not dedicated)
  • Register Write Protection
  • Arm TrustZone Technology