Jump to main content
Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, 500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB, PCI 5.0 Pre-Certified SAMA5D2 Series
Search
Product Pages
ATSAMA5D21
ATSAMA5D22
ATSAMA5D23
ATSAMA5D24
ATSAMA5D26
ATSAMA5D27
ATSAMA5D28
Home
15
Debug and Test Features
15.6
Functional Description
SAMA5D2 Series
Introduction
Features
Description
1
Configuration Summary
2
Block Diagram
3
Signal Description
4
Microchip Recommended Power Management Solutions
5
Safety and Security Features
6
Package and Pinout
7
Power Considerations
8
Memories
9
Event System
10
System Controller
11
Peripherals
12
Chip Identifier (CHIPID)
13
Cortex-A5 Processor (ARM)
14
L2 Cache Controller (L2CC)
15
Debug and Test Features
15.1
Description
15.2
Embedded Characteristics
15.3
Debug and Test Block Diagrams
15.4
Application Examples
15.5
Debug and Test Pin Description
15.6
Functional Description
15.6.1
Test Pin
15.6.2
EmbeddedICE
15.6.3
JTAG Signal Description
15.6.4
IEEE 1149.1 JTAG Boundary Scan
15.7
Boundary JTAG ID Register
Boundary JTAG ID Register
15.8
Cortex-A5 DP Identification Code Register IDCODE
16
Standard Boot Strategies
17
CPU System Bus Matrix (CPUMX)
18
Matrix (H64MX/H32MX)
19
Special Function Registers (SFR)
20
Special Function Registers Backup (SFRBU)
21
Advanced Interrupt Controller (AIC)
22
Watchdog Timer (WDT)
23
Reset Controller (RSTC)
24
Shutdown Controller (SHDWC)
25
Periodic Interval Timer (PIT)
26
Real-time Clock (RTC)
27
System Controller Write Protection (SYSCWP)
28
Slow Clock Controller (SCKC)
29
Peripheral Touch Controller (PTC)
30
Low Power Asynchronous Receiver (RXLP)
31
Clock Generator
32
Power Management Controller (PMC)
33
Parallel Input/Output Controller (PIO)
34
External Memories
35
DDR-SDRAM Controller (MPDDRC)
36
Static Memory Controller (SMC)
37
DMA Controller (XDMAC)
38
LCD Controller (LCDC)
39
Ethernet MAC (GMAC)
40
USB Device High Speed Port (UDPHS)
41
USB Host High Speed Port (UHPHS)
42
Audio Class D Amplifier (CLASSD)
43
Inter-IC Sound Controller (I2SC)
44
Synchronous Serial Controller (SSC)
45
Two-wire Interface (TWIHS)
46
Flexible Serial Communication Controller (FLEXCOM)
47
Universal Asynchronous Receiver Transmitter (UART)
48
Serial Peripheral Interface (SPI)
49
Quad Serial Peripheral Interface (QSPI)
50
Secure Digital MultiMedia Card Controller (SDMMC)
51
Image Sensor Controller (ISC)
52
Controller Area Network (MCAN)
53
Timer Counter (TC)
54
Pulse Density Modulation Interface Controller (PDMIC)
55
Pulse Width Modulation Controller (PWM)
56
Secure Fuse Controller (SFC)
57
Integrity Check Monitor (ICM)
58
Advanced Encryption Standard Bridge (AESB)
59
Advanced Encryption Standard (AES)
60
Secure Hash Algorithm (SHA)
61
Triple Data Encryption Standard (TDES)
62
True Random Number Generator (TRNG)
63
Analog Comparator Controller (ACC)
64
Security Module (SECUMOD)
65
Analog-to-Digital Controller (ADC)
66
Electrical Characteristics
67
Mechanical Characteristics
68
Marking
69
Ordering Information
70
Revision History
Microchip Information
15.6 Functional Description