41.9 UHPHS Asynchronous List Address Register

This 32-bit register contains the address of the next asynchronous queue head to be executed. Bits [4:0] of this register cannot be modified by system software and will always return a zero when read. The memory structure referenced by this physical memory pointer is assumed to be 32-byte (cache line) aligned. This register must be written as a DWord. Byte writes produce undefined results.

Name: UHPHS_ASYNCLISTADDR
Offset: 0x28
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 LPL[26:19] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 LPL[18:11] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 LPL[10:3] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 LPL[2:0]      
Access R/WR/WR/W 
Reset 000 

Bits 31:5 – LPL[26:0] Link Pointer Low

These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH).