35.5.4.2 Power-Down Mode
This mode is activated by configuring the Low-power Command bit (LPCB) to 2 in the MPDDRC Low-Power Register (MPDDRC_LPR).
Power-down mode is used when no access to the DDR-SDRAM device is possible. In this mode, power consumption is greater than in Self-refresh mode. This state is similar to Normal mode (no Low-power mode/no Self-refresh mode), but the CKE pin is low and the input and output buffers are deactivated as soon the DDR-SDRAM device is no longer accessible. In contrast to Self-refresh mode, the DDR-SDRAM device cannot remain in Low-power mode longer than one refresh period (64 ms/32 ms). As no auto-refresh operations are performed in this mode, the MPDDRC carries out the refresh operation. For the low-power DDR-SDRAM devices, a NOP command must be generated for a minimum period defined in the TXP field of the Timing Parameter 1 register (MPDDRC_TPR1). For DDR-SDRAM devices, a NOP command must be generated for a minimum period defined in the TXP field of MPDDRC_TPR1 (see MPDDRC Timing Parameter 1 Register) and in the TXARD and TXARDS fields of MPDDRC_TPR2 (see MPDDRC Timing Parameter 2 Register) for DDR2_SDRAM devices. In addition, low-power DDR-SDRAM and DDR-SDRAM must remain in Power-down mode for a minimum period corresponding to tCKE, tPD, etc. (refer to the memory device data sheet).
The exit procedure is faster than in Self-refresh mode. See the following figure. The MPDDRC returns to Power-down mode as soon as the DDR-SDRAM device is not selected. It is possible to define when Power-down mode is enabled by configuring the TIMEOUT field in the MPDDRC_LPR:
0: Power-down mode is enabled as soon as the DDR-SDRAM device is not selected.
1: Power-down mode is enabled 64 clock cycles after completion of the last access.
2: Power-down mode is enabled 128 clock cycles after completion of the last access.