38.7.136 High-End Overlay Configuration Register 41
Name: | LCDC_HEOCFG41 |
Offset: | 0x00000430 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
YPHIDEF[2:0] | |||||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
XPHIDEF[2:0] | |||||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bits 18:16 – YPHIDEF[2:0] Vertical Filter Phase Offset
XPHIDEF defines the index of the first coefficient set used when the vertical resampling operation is started.
Bits 2:0 – XPHIDEF[2:0] Horizontal Filter Phase Offset
XPHIDEF defines the index of the first coefficient set used when the horizontal resampling operation is started.