39.111 GMAC Interrupt Status Register Priority Queue x
| Name: | GMAC_ISRPQx |
| Offset: | 0x0400 + (x-1)*0x04 [x=1..2] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HRESP | ROVR | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TCOMP | TFC | RLEX | RXUBR | RCOMP | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 11 – HRESP System Bus Error
Bit 10 – ROVR Receive Overrun
Bit 7 – TCOMP Transmit Complete
Bit 6 – TFC Transmit Frame Corruption Due to System Bus Error
Set if an error occurs whilst midway through reading transmit frame from the system bus, including system buss errors and buffers exhausted mid frame.