8.2.3 Supported Memories on Static Memories and NAND Flash Interfaces

The Static Memory Controller is dedicated to interfacing external memory devices:

  • Asynchronous SRAM-like memories and parallel peripherals
  • NAND Flash (MLC and SLC) 8-bit datapath

The Static Memory Controller is able to drive up to four chip select. NCS3 is dedicated to the NAND Flash control.

The HSMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands and address cycles to the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the processor overhead.

In order to improve overall system performance, the DATA phase of the transfer can be DMA-assisted. The static memory embeds the NAND Flash Error Correcting Code controller with the following features:

  • Algorithm based on BCH codes
  • Supports also SLC 1-bit (BCH 2-bit), SLC 4-bit (BCH 4-bit)
  • Programmable Error Correcting Capability
    • 2-bit, 4-bit, 8-bit and 16-bit errors for 512 bytes/sector (4-Kbyte page)
    • 24-bit error for 1024 bytes/sector (8-Kbyte page)
  • Programmable sector size: 512 bytes or 1024 bytes
  • Programmable number of sectors per page: 1, 2, 4 or 8 blocks of data per page
  • Programmable spare area size
  • Supports spare area ECC protection
  • Supports 8-Kbyte page size using 1024 bytes/sector and 4-Kbyte page size using 512 bytes/sector
  • Error detection is interrupt-driven
  • Provides hardware acceleration for error location
  • Finds roots of error-locator polynomial
  • Programmable number of roots