38.7 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	LCDC_LCDCFG0	31:24
		23:16	CLKDIV[7:0]
		15:8			CGDISPP		CGDISHEO	CGDISOVR2	CGDISOVR1	CGDISBASE
		7:0					CLKPWMSEL	CLKSEL		CLKPOL
0x04	LCDC_LCDCFG1	31:24							VSPW[9:8]
		23:16	VSPW[7:0]
		15:8							HSPW[9:8]
		7:0	HSPW[7:0]
0x08	LCDC_LCDCFG2	31:24							VBPW[9:8]
		23:16	VBPW[7:0]
		15:8							VFPW[9:8]
		7:0	VFPW[7:0]
0x0C	LCDC_LCDCFG3	31:24							HBPW[9:8]
		23:16	HBPW[7:0]
		15:8							HFPW[9:8]
		7:0	HFPW[7:0]
0x10	LCDC_LCDCFG4	31:24						RPF[10:8]
		23:16	RPF[7:0]
		15:8						PPL[10:8]
		7:0	PPL[7:0]
0x14	LCDC_LCDCFG5	31:24
		23:16	GUARDTIME[7:0]
		15:8			VSPHO	VSPSU		PP	MODE[1:0]
		7:0	DISPDLY	DITHER		DISPPOL	VSPDLYE	VSPDLYS	VSPOL	HSPOL
0x18	LCDC_LCDCFG6	31:24
		23:16
		15:8	PWMCVAL[7:0]
		7:0				PWMPOL		PWMPS[2:0]
0x1C ... 0x1F	Reserved
0x20	LCDC_LCDEN	31:24
		23:16
		15:8
		7:0					PWMEN	DISPEN	SYNCEN	CLKEN
0x24	LCDC_LCDDIS	31:24
		23:16
		15:8					PWMRST	DISPRST	SYNCRST	CLKRST
		7:0					PWMDIS	DISPDIS	SYNCDIS	CLKDIS
0x28	LCDC_LCDSR	31:24
		23:16
		15:8
		7:0				SIPSTS	PWMSTS	DISPSTS	LCDSTS	CLKSTS
0x2C	LCDC_LCDIER	31:24
		23:16
		15:8			PPIE		HEOIE	OVR2IE	OVR1IE	BASEIE
		7:0				FIFOERRIE		DISPIE	DISIE	SOFIE
0x30	LCDC_LCDIDR	31:24
		23:16
		15:8			PPID		HEOID	OVR2ID	OVR1ID	BASEID
		7:0				FIFOERRID		DISPID	DISID	SOFID
0x34	LCDC_LCDIMR	31:24
		23:16
		15:8			PPIM		HEOIM	OVR2IM	OVR1IM	BASEIM
		7:0				FIFOERRIM		DISPIM	DISIM	SOFIM
0x38	LCDC_LCDISR	31:24
		23:16
		15:8			PP		HEO	OVR2	OVR1	BASE
		7:0				FIFOERR		DISP	DIS	SOF
0x3C	LCDC_ATTR	31:24
		23:16
		15:8			PPA2Q		HEOA2Q	OVR2A2Q	OVR1A2Q	BASEA2Q
		7:0			PP		HEO	OVR2	OVR1	BASE
0x40	LCDC_BASECHER	31:24
		23:16
		15:8
		7:0						A2QEN	UPDATEEN	CHEN
0x44	LCDC_BASECHDR	31:24
		23:16
		15:8								CHRST
		7:0								CHDIS
0x48	LCDC_BASECHSR	31:24
		23:16
		15:8
		7:0						A2QSR	UPDATESR	CHSR
0x4C	LCDC_BASEIER	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x50	LCDC_BASEIDR	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x54	LCDC_BASEIMR	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x58	LCDC_BASEISR	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x5C	LCDC_BASEHEAD	31:24	HEAD[29:22]
		23:16	HEAD[21:14]
		15:8	HEAD[13:6]
		7:0	HEAD[5:0]
0x60	LCDC_BASEADDR	31:24	ADDR[31:24]
		23:16	ADDR[23:16]
		15:8	ADDR[15:8]
		7:0	ADDR[7:0]
0x64	LCDC_BASECTRL	31:24
		23:16
		15:8
		7:0			DONEIEN	ADDIEN	DSCRIEN	DMAIEN	LFETCH	DFETCH
0x68	LCDC_BASENEXT	31:24	NEXT[31:24]
		23:16	NEXT[23:16]
		15:8	NEXT[15:8]
		7:0	NEXT[7:0]
0x6C	LCDC_BASECFG0	31:24
		23:16
		15:8								DLBO
		7:0			BLEN[1:0]					SIF
0x70	LCDC_BASECFG1	31:24
		23:16
		15:8							CLUTMODE[1:0]
		7:0	RGBMODE[3:0]							CLUTEN
0x74	LCDC_BASECFG2	31:24	XSTRIDE[31:24]
		23:16	XSTRIDE[23:16]
		15:8	XSTRIDE[15:8]
		7:0	XSTRIDE[7:0]
0x78	LCDC_BASECFG3	31:24
		23:16	RDEF[7:0]
		15:8	GDEF[7:0]
		7:0	BDEF[7:0]
0x7C	LCDC_BASECFG4	31:24
		23:16
		15:8					DISCEN		REP	DMA
		7:0
0x80	LCDC_BASECFG5	31:24						DISCYPOS[10:8]
		23:16	DISCYPOS[7:0]
		15:8						DISCXPOS[10:8]
		7:0	DISCXPOS[7:0]
0x84	LCDC_BASECFG6	31:24						DISCYSIZE[10:8]
		23:16	DISCYSIZE[7:0]
		15:8						DISCXSIZE[10:8]
		7:0	DISCXSIZE[7:0]
0x88 ... 0x013F	Reserved
0x0140	LCDC_OVR1CHER	31:24
		23:16
		15:8
		7:0						A2QEN	UPDATEEN	CHEN
0x0144	LCDC_OVR1CHDR	31:24
		23:16
		15:8								CHRST
		7:0								CHDIS
0x0148	LCDC_OVR1CHSR	31:24
		23:16
		15:8
		7:0						A2QSR	UPDATESR	CHSR
0x014C	LCDC_OVR1IER	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x0150	LCDC_OVR1IDR	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x0154	LCDC_OVR1IMR	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x0158	LCDC_OVR1ISR	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x015C	LCDC_OVR1HEAD	31:24	HEAD[29:22]
		23:16	HEAD[21:14]
		15:8	HEAD[13:6]
		7:0	HEAD[5:0]
0x0160	LCDC_OVR1ADDR	31:24	ADDR[31:24]
		23:16	ADDR[23:16]
		15:8	ADDR[15:8]
		7:0	ADDR[7:0]
0x0164	LCDC_OVR1CTRL	31:24
		23:16
		15:8
		7:0			DONEIEN	ADDIEN	DSCRIEN	DMAIEN	LFETCH	DFETCH
0x0168	LCDC_OVR1NEXT	31:24	NEXT[31:24]
		23:16	NEXT[23:16]
		15:8	NEXT[15:8]
		7:0	NEXT[7:0]
0x016C	LCDC_OVR1CFG0	31:24
		23:16
		15:8			LOCKDIS	ROTDIS				DLBO
		7:0			BLEN[1:0]					SIF
0x0170	LCDC_OVR1CFG1	31:24
		23:16
		15:8							CLUTMODE[1:0]
		7:0	RGBMODE[3:0]							CLUTEN
0x0174	LCDC_OVR1CFG2	31:24						YPOS[10:8]
		23:16	YPOS[7:0]
		15:8						XPOS[10:8]
		7:0	XPOS[7:0]
0x0178	LCDC_OVR1CFG3	31:24						YSIZE[10:8]
		23:16	YSIZE[7:0]
		15:8						XSIZE[10:8]
		7:0	XSIZE[7:0]
0x017C	LCDC_OVR1CFG4	31:24	XSTRIDE[31:24]
		23:16	XSTRIDE[23:16]
		15:8	XSTRIDE[15:8]
		7:0	XSTRIDE[7:0]
0x0180	LCDC_OVR1CFG5	31:24	PSTRIDE[31:24]
		23:16	PSTRIDE[23:16]
		15:8	PSTRIDE[15:8]
		7:0	PSTRIDE[7:0]
0x0184	LCDC_OVR1CFG6	31:24
		23:16	RDEF[7:0]
		15:8	GDEF[7:0]
		7:0	BDEF[7:0]
0x0188	LCDC_OVR1CFG7	31:24
		23:16	RKEY[7:0]
		15:8	GKEY[7:0]
		7:0	BKEY[7:0]
0x018C	LCDC_OVR1CFG8	31:24
		23:16	RMASK[7:0]
		15:8	GMASK[7:0]
		7:0	BMASK[7:0]
0x0190	LCDC_OVR1CFG9	31:24
		23:16	GA[7:0]
		15:8						DSTKEY	REP	DMA
		7:0	OVR	LAEN	GAEN	REVALPHA	ITER	ITER2BL	INV	CRKEY
0x0194 ... 0x023F	Reserved
0x0240	LCDC_OVR2CHER	31:24
		23:16
		15:8
		7:0						A2QEN	UPDATEEN	CHEN
0x0244	LCDC_OVR2CHDR	31:24
		23:16
		15:8								CHRST
		7:0								CHDIS
0x0248	LCDC_OVR2CHSR	31:24
		23:16
		15:8
		7:0						A2QSR	UPDATESR	CHSR
0x024C	LCDC_OVR2IER	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x0250	LCDC_OVR2IDR	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x0254	LCDC_OVR2IMR	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x0258	LCDC_OVR2ISR	31:24
		23:16
		15:8
		7:0		OVR	DONE	ADD	DSCR	DMA
0x025C	LCDC_OVR2HEAD	31:24	HEAD[29:22]
		23:16	HEAD[21:14]
		15:8	HEAD[13:6]
		7:0	HEAD[5:0]
0x0260	LCDC_OVR2ADDR	31:24	ADDR[31:24]
		23:16	ADDR[23:16]
		15:8	ADDR[15:8]
		7:0	ADDR[7:0]
0x0264	LCDC_OVR2CTRL	31:24
		23:16
		15:8
		7:0			DONEIEN	ADDIEN	DSCRIEN	DMAIEN	LFETCH	DFETCH
0x0268	LCDC_OVR2NEXT	31:24	NEXT[31:24]
		23:16	NEXT[23:16]
		15:8	NEXT[15:8]
		7:0	NEXT[7:0]
0x026C	LCDC_OVR2CFG0	31:24
		23:16
		15:8			LOCKDIS	ROTDIS				DLBO
		7:0			BLEN[1:0]					SIF
0x0270	LCDC_OVR2CFG1	31:24
		23:16
		15:8							CLUTMODE[1:0]
		7:0	RGBMODE[3:0]							CLUTEN
0x0274	LCDC_OVR2CFG2	31:24						YPOS[10:8]
		23:16	YPOS[7:0]
		15:8						XPOS[10:8]
		7:0	XPOS[7:0]
0x0278	LCDC_OVR2CFG3	31:24						YSIZE[10:8]
		23:16	YSIZE[7:0]
		15:8						XSIZE[10:8]
		7:0	XSIZE[7:0]
0x027C	LCDC_OVR2CFG4	31:24	XSTRIDE[31:24]
		23:16	XSTRIDE[23:16]
		15:8	XSTRIDE[15:8]
		7:0	XSTRIDE[7:0]
0x0280	LCDC_OVR2CFG5	31:24	PSTRIDE[31:24]
		23:16	PSTRIDE[23:16]
		15:8	PSTRIDE[15:8]
		7:0	PSTRIDE[7:0]
0x0284	LCDC_OVR2CFG6	31:24
		23:16	RDEF[7:0]
		15:8	GDEF[7:0]
		7:0	BDEF[7:0]
0x0288	LCDC_OVR2CFG7	31:24
		23:16	RKEY[7:0]
		15:8	GKEY[7:0]
		7:0	BKEY[7:0]
0x028C	LCDC_OVR2CFG8	31:24
		23:16	RMASK[7:0]
		15:8	GMASK[7:0]
		7:0	BMASK[7:0]
0x0290	LCDC_OVR2CFG9	31:24
		23:16	GA[7:0]
		15:8						DSTKEY	REP	DMA
		7:0	OVR	LAEN	GAEN	REVALPHA	ITER	ITER2BL	INV	CRKEY
0x0294 ... 0x033F	Reserved
0x0340	LCDC_HEOCHER	31:24
		23:16
		15:8
		7:0						A2QEN	UPDATEEN	CHEN
0x0344	LCDC_HEOCHDR	31:24
		23:16
		15:8								CHRST
		7:0								CHDIS
0x0348	LCDC_HEOCHSR	31:24
		23:16
		15:8
		7:0						A2QSR	UPDATESR	CHSR
0x034C	LCDC_HEOIER	31:24
		23:16		VOVR	VDONE	VADD	VDSCR	VDMA
		15:8		UOVR	UDONE	UADD	UDSCR	UDMA
		7:0		OVR	DONE	ADD	DSCR	DMA
0x0350	LCDC_HEOIDR	31:24
		23:16		VOVR	VDONE	VADD	VDSCR	VDMA
		15:8		UOVR	UDONE	UADD	UDSCR	UDMA
		7:0		OVR	DONE	ADD	DSCR	DMA
0x0354	LCDC_HEOIMR	31:24
		23:16		VOVR	VDONE	VADD	VDSCR	VDMA
		15:8		UOVR	UDONE	UADD	UDSCR	UDMA
		7:0		OVR	DONE	ADD	DSCR	DMA
0x0358	LCDC_HEOISR	31:24
		23:16		VOVR	VDONE	VADD	VDSCR	VDMA
		15:8		UOVR	UDONE	UADD	UDSCR	UDMA
		7:0		OVR	DONE	ADD	DSCR	DMA
0x035C	LCDC_HEOHEAD	31:24	HEAD[29:22]
		23:16	HEAD[21:14]
		15:8	HEAD[13:6]
		7:0	HEAD[5:0]
0x0360	LCDC_HEOADDR	31:24	ADDR[31:24]
		23:16	ADDR[23:16]
		15:8	ADDR[15:8]
		7:0	ADDR[7:0]
0x0364	LCDC_HEOCTRL	31:24
		23:16
		15:8
		7:0			DONEIEN	ADDIEN	DSCRIEN	DMAIEN	LFETCH	DFETCH
0x0368	LCDC_HEONEXT	31:24	NEXT[31:24]
		23:16	NEXT[23:16]
		15:8	NEXT[15:8]
		7:0	NEXT[7:0]
0x036C	LCDC_HEOUHEAD	31:24	UHEAD[31:24]
		23:16	UHEAD[23:16]
		15:8	UHEAD[15:8]
		7:0	UHEAD[7:0]
0x0370	LCDC_HEOUADDR	31:24	UADDR[31:24]
		23:16	UADDR[23:16]
		15:8	UADDR[15:8]
		7:0	UADDR[7:0]
0x0374	LCDC_HEOUCTRL	31:24
		23:16
		15:8
		7:0			UDONEIEN	UADDIEN	UDSCRIEN	UDMAIEN		UDFETCH
0x0378	LCDC_HEOUNEXT	31:24	UNEXT[31:24]
		23:16	UNEXT[23:16]
		15:8	UNEXT[15:8]
		7:0	UNEXT[7:0]
0x037C	LCDC_HEOVHEAD	31:24	VHEAD[31:24]
		23:16	VHEAD[23:16]
		15:8	VHEAD[15:8]
		7:0	VHEAD[7:0]
0x0380	LCDC_HEOVADDR	31:24	VADDR[31:24]
		23:16	VADDR[23:16]
		15:8	VADDR[15:8]
		7:0	VADDR[7:0]
0x0384	LCDC_HEOVCTRL	31:24
		23:16
		15:8
		7:0			VDONEIEN	VADDIEN	VDSCRIEN	VDMAIEN		VDFETCH
0x0388	LCDC_HEOVNEXT	31:24	VNEXT[31:24]
		23:16	VNEXT[23:16]
		15:8	VNEXT[15:8]
		7:0	VNEXT[7:0]
0x038C	LCDC_HEOCFG0	31:24
		23:16
		15:8			LOCKDIS	ROTDIS				DLBO
		7:0	BLENUV[1:0]		BLEN[1:0]					SIF
0x0390	LCDC_HEOCFG1	31:24
		23:16				DSCALEOPT			YUV422SWP	YUV422ROT
		15:8	YUVMODE[3:0]						CLUTMODE[1:0]
		7:0	RGBMODE[3:0]						YUVEN	CLUTEN
0x0394	LCDC_HEOCFG2	31:24						YPOS[10:8]
		23:16	YPOS[7:0]
		15:8						XPOS[10:8]
		7:0	XPOS[7:0]
0x0398	LCDC_HEOCFG3	31:24						YSIZE[10:8]
		23:16	YSIZE[7:0]
		15:8						XSIZE[10:8]
		7:0	XSIZE[7:0]
0x039C	LCDC_HEOCFG4	31:24						YMEMSIZE[10:8]
		23:16	YMEMSIZE[7:0]
		15:8						XMEMSIZE[10:8]
		7:0	XMEMSIZE[7:0]
0x03A0	LCDC_HEOCFG5	31:24	XSTRIDE[31:24]
		23:16	XSTRIDE[23:16]
		15:8	XSTRIDE[15:8]
		7:0	XSTRIDE[7:0]
0x03A4	LCDC_HEOCFG6	31:24	PSTRIDE[31:24]
		23:16	PSTRIDE[23:16]
		15:8	PSTRIDE[15:8]
		7:0	PSTRIDE[7:0]
0x03A8	LCDC_HEOCFG7	31:24	UVXSTRIDE[31:24]
		23:16	UVXSTRIDE[23:16]
		15:8	UVXSTRIDE[15:8]
		7:0	UVXSTRIDE[7:0]
0x03AC	LCDC_HEOCFG8	31:24	UVPSTRIDE[31:24]
		23:16	UVPSTRIDE[23:16]
		15:8	UVPSTRIDE[15:8]
		7:0	UVPSTRIDE[7:0]
0x03B0	LCDC_HEOCFG9	31:24
		23:16	RDEF[7:0]
		15:8	GDEF[7:0]
		7:0	BDEF[7:0]
0x03B4	LCDC_HEOCFG10	31:24
		23:16	RKEY[7:0]
		15:8	GKEY[7:0]
		7:0	BKEY[7:0]
0x03B8	LCDC_HEOCFG11	31:24
		23:16	RMASK[7:0]
		15:8	GMASK[7:0]
		7:0	BMASK[7:0]
0x03BC	LCDC_HEOCFG12	31:24
		23:16	GA[7:0]
		15:8				VIDPRI		DSTKEY	REP	DMA
		7:0	OVR	LAEN	GAEN	REVALPHA	ITER	ITER2BL	INV	CRKEY
0x03C0	LCDC_HEOCFG13	31:24	SCALEN		YFACTOR[13:8]
		23:16	YFACTOR[7:0]
		15:8			XFACTOR[13:8]
		7:0	XFACTOR[7:0]
0x03C4	LCDC_HEOCFG14	31:24		CSCYOFF	CSCRV[9:4]
		23:16	CSCRV[3:0]				CSCRU[9:6]
		15:8	CSCRU[5:0]						CSCRY[9:8]
		7:0	CSCRY[7:0]
0x03C8	LCDC_HEOCFG15	31:24		CSCUOFF	CSCGV[9:4]
		23:16	CSCGV[3:0]				CSCGU[9:6]
		15:8	CSCGU[5:0]						CSCGY[9:8]
		7:0	CSCGY[7:0]
0x03CC	LCDC_HEOCFG16	31:24		CSCVOFF	CSCBV[9:4]
		23:16	CSCBV[3:0]				CSCBU[9:6]
		15:8	CSCBU[5:0]						CSCBY[9:8]
		7:0	CSCBY[7:0]
0x03D0	LCDC_HEOCFG17	31:24	XPHI0COEFF3[7:0]
		23:16	XPHI0COEFF2[7:0]
		15:8	XPHI0COEFF1[7:0]
		7:0	XPHI0COEFF0[7:0]
0x03D4	LCDC_HEOCFG18	31:24
		23:16
		15:8
		7:0	XPHI0COEFF4[7:0]
0x03D8	LCDC_HEOCFG19	31:24	XPHI1COEFF3[7:0]
		23:16	XPHI1COEFF2[7:0]
		15:8	XPHI1COEFF1[7:0]
		7:0	XPHI1COEFF0[7:0]
0x03DC	LCDC_HEOCFG20	31:24
		23:16
		15:8
		7:0	XPHI1COEFF4[7:0]
0x03E0	LCDC_HEOCFG21	31:24	XPHI2COEFF3[7:0]
		23:16	XPHI2COEFF2[7:0]
		15:8	XPHI2COEFF1[7:0]
		7:0	XPHI2COEFF0[7:0]
0x03E4	LCDC_HEOCFG22	31:24
		23:16
		15:8
		7:0	XPHI2COEFF4[7:0]
0x03E8	LCDC_HEOCFG23	31:24	XPHI3COEFF3[7:0]
		23:16	XPHI3COEFF2[7:0]
		15:8	XPHI3COEFF1[7:0]
		7:0	XPHI3COEFF0[7:0]
0x03EC	LCDC_HEOCFG24	31:24
		23:16
		15:8
		7:0	XPHI3COEFF4[7:0]
0x03F0	LCDC_HEOCFG25	31:24	XPHI4COEFF3[7:0]
		23:16	XPHI4COEFF2[7:0]
		15:8	XPHI4COEFF1[7:0]
		7:0	XPHI4COEFF0[7:0]
0x03F4	LCDC_HEOCFG26	31:24
		23:16
		15:8
		7:0	XPHI4COEFF4[7:0]
0x03F8	LCDC_HEOCFG27	31:24	XPHI5COEFF3[7:0]
		23:16	XPHI5COEFF2[7:0]
		15:8	XPHI5COEFF1[7:0]
		7:0	XPHI5COEFF0[7:0]
0x03FC	LCDC_HEOCFG28	31:24
		23:16
		15:8
		7:0	XPHI5COEFF4[7:0]
0x0400	LCDC_HEOCFG29	31:24	XPHI6COEFF3[7:0]
		23:16	XPHI6COEFF2[7:0]
		15:8	XPHI6COEFF1[7:0]
		7:0	XPHI6COEFF0[7:0]
0x0404	LCDC_HEOCFG30	31:24
		23:16
		15:8
		7:0	XPHI6COEFF4[7:0]
0x0408	LCDC_HEOCFG31	31:24	XPHI7COEFF3[7:0]
		23:16	XPHI7COEFF2[7:0]
		15:8	XPHI7COEFF1[7:0]
		7:0	XPHI7COEFF0[7:0]
0x040C	LCDC_HEOCFG32	31:24
		23:16
		15:8
		7:0	XPHI7COEFF4[7:0]
0x0410	LCDC_HEOCFG33	31:24
		23:16	YPHI0COEFF2[7:0]
		15:8	YPHI0COEFF1[7:0]
		7:0	YPHI0COEFF0[7:0]
0x0414	LCDC_HEOCFG34	31:24
		23:16	YPHI1COEFF2[7:0]
		15:8	YPHI1COEFF1[7:0]
		7:0	YPHI1COEFF0[7:0]
0x0418	LCDC_HEOCFG35	31:24
		23:16	YPHI2COEFF2[7:0]
		15:8	YPHI2COEFF1[7:0]
		7:0	YPHI2COEFF0[7:0]
0x041C	LCDC_HEOCFG36	31:24
		23:16	YPHI3COEFF2[7:0]
		15:8	YPHI3COEFF1[7:0]
		7:0	YPHI3COEFF0[7:0]
0x0420	LCDC_HEOCFG37	31:24
		23:16	YPHI4COEFF2[7:0]
		15:8	YPHI4COEFF1[7:0]
		7:0	YPHI4COEFF0[7:0]
0x0424	LCDC_HEOCFG38	31:24
		23:16	YPHI5COEFF2[7:0]
		15:8	YPHI5COEFF1[7:0]
		7:0	YPHI5COEFF0[7:0]
0x0428	LCDC_HEOCFG39	31:24
		23:16	YPHI6COEFF2[7:0]
		15:8	YPHI6COEFF1[7:0]
		7:0	YPHI6COEFF0[7:0]
0x042C	LCDC_HEOCFG40	31:24
		23:16	YPHI7COEFF2[7:0]
		15:8	YPHI7COEFF1[7:0]
		7:0	YPHI7COEFF0[7:0]
0x0430	LCDC_HEOCFG41	31:24
		23:16						YPHIDEF[2:0]
		15:8
		7:0						XPHIDEF[2:0]
0x0434 ... 0x053F	Reserved
0x0540	LCDC_PPCHER	31:24
		23:16
		15:8
		7:0						A2QEN	UPDATEEN	CHEN
0x0544	LCDC_PPCHDR	31:24
		23:16
		15:8								CHRST
		7:0								CHDIS
0x0548	LCDC_PPCHSR	31:24
		23:16
		15:8
		7:0						A2QSR	UPDATESR	CHSR
0x054C	LCDC_PPIER	31:24
		23:16
		15:8
		7:0			DONE	ADD	DSCR	DMA
0x0550	LCDC_PPIDR	31:24
		23:16
		15:8
		7:0			DONE	ADD	DSCR	DMA
0x0554	LCDC_PPIMR	31:24
		23:16
		15:8
		7:0			DONE	ADD	DSCR	DMA
0x0558	LCDC_PPISR	31:24
		23:16
		15:8
		7:0			DONE	ADD	DSCR	DMA
0x055C	LCDC_PPHEAD	31:24	HEAD[29:22]
		23:16	HEAD[21:14]
		15:8	HEAD[13:6]
		7:0	HEAD[5:0]
0x0560	LCDC_PPADDR	31:24	ADDR[31:24]
		23:16	ADDR[23:16]
		15:8	ADDR[15:8]
		7:0	ADDR[7:0]
0x0564	LCDC_PPCTRL	31:24
		23:16
		15:8
		7:0			DONEIEN	ADDIEN	DSCRIEN	DMAIEN		DFETCH
0x0568	LCDC_PPNEXT	31:24	NEXT[31:24]
		23:16	NEXT[23:16]
		15:8	NEXT[15:8]
		7:0	NEXT[7:0]
0x056C	LCDC_PPCFG0	31:24
		23:16
		15:8								DLBO
		7:0			BLEN[1:0]					SIF
0x0570	LCDC_PPCFG1	31:24
		23:16
		15:8
		7:0				ITUBT601		PPMODE[2:0]
0x0574	LCDC_PPCFG2	31:24	XSTRIDE[31:24]
		23:16	XSTRIDE[23:16]
		15:8	XSTRIDE[15:8]
		7:0	XSTRIDE[7:0]
0x0578	LCDC_PPCFG3	31:24		CSCYOFF	CSCYB[9:4]
		23:16	CSCYB[3:0]				CSCYG[9:6]
		15:8	CSCYG[5:0]						CSCYR[9:8]
		7:0	CSCYR[7:0]
0x057C	LCDC_PPCFG4	31:24		CSCUOFF	CSCUB[9:4]
		23:16	CSCUB[3:0]				CSCUG[9:6]
		15:8	CSCUG[5:0]						CSCUR[9:8]
		7:0	CSCUR[7:0]
0x0580	LCDC_PPCFG5	31:24		CSCVOFF	CSCVB[9:4]
		23:16	CSCVB[3:0]				CSCVG[9:6]
		15:8	CSCVG[5:0]						CSCVR[9:8]
		7:0	CSCVR[7:0]
0x0584 ... 0x05FF	Reserved
0x0600	LCDC_BASECLUT0	31:24
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
...
0x09FC	LCDC_BASECLUT255	31:24
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
0x0A00	LCDC_OVR1CLUT0	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
...
0x0DFC	LCDC_OVR1CLUT255	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
0x0E00	LCDC_OVR2CLUT0	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
...
0x11FC	LCDC_OVR2CLUT255	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
0x1200	LCDC_HEOCLUT0	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
...
0x15FC	LCDC_HEOCLUT255	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]

SAMA5D2 Series

38.7 Register Summary