57.6.6 ICM Interrupt Mask Register
| Name: | ICM_IMR |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| URAD | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RSU[3:0] | REC[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RWC[3:0] | RBE[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RDM[3:0] | RHC[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 24 – URAD Undefined Register Access Detection Interrupt Mask
| Value | Description |
|---|---|
| 0 | Interrupt is disabled |
| 1 | Interrupt is enabled. |
Bits 23:20 – RSU[3:0] Region Status Updated Interrupt Mask
| Value | Description |
|---|---|
| 0 | When RSU[i] is set to zero, the interrupt is disabled for region i. |
| 1 | When RSU[i] is set to one, the interrupt is enabled for region i. |
Bits 19:16 – REC[3:0] Region End Bit Condition Detected Interrupt Mask
| Value | Description |
|---|---|
| 0 | When REC[i] is set to zero, the interrupt is disabled for region i. |
| 1 | When REC[i] is set to one, the interrupt is enabled for region i. |
Bits 15:12 – RWC[3:0] Region Wrap Condition Detected Interrupt Mask
| Value | Description |
|---|---|
| 0 | When RWC[i] is set to zero, the interrupt is disabled for region i. |
| 1 | When RWC[i] is set to one, the interrupt is enabled for region i. |
Bits 11:8 – RBE[3:0] Region Bus Error Interrupt Mask
| Value | Description |
|---|---|
| 0 | When RBE[i] is set to zero, the interrupt is disabled for region i. |
| 1 | When RBE[i] is set to one, the interrupt is enabled for region i. |
Bits 7:4 – RDM[3:0] Region Digest Mismatch Interrupt Mask
| Value | Description |
|---|---|
| 0 | When RDM[i] is set to zero, the interrupt is disabled for region i. |
| 1 | When RDM[i] is set to one, the interrupt is enabled for region i. |
Bits 3:0 – RHC[3:0] Region Hash Completed Interrupt Mask
| Value | Description |
|---|---|
| 0 | When RHC[i] is set to zero, the interrupt is disabled for region i. |
| 1 | When RHC[i] is set to one, the interrupt is enabled for region i. |