39.2 Embedded Characteristics

  • Compatible with IEEE Standard 802.3
  • 10, 100 Mbps Operation
  • Supports 802.1Qav Traffic Shaping on Two Highest Priority Queues
  • Full and Half Duplex Operation at all Supported Speeds of Operation
  • Statistics Counter Registers for RMON/MIB
  • MII/RMII Interface to the Physical Layer
  • Integrated Physical Coding
  • Direct Memory Access (DMA) Interface to External Memory
  • Support for 3 Priority Queues
  • 8 Kbytes Transmit Local Memory and 4 Kbytes Receive Local Memory (refer to Table 39-4 for queue-specific sizes)
  • Programmable Burst Length and Endianism for DMA
  • Interrupt Generation to Signal Receive and Transmit Completion, Errors or Other Events
  • Automatic Pad and Cyclic Redundancy Check (CRC) Generation on Transmitted Frames
  • Automatic Discard of Frames Received with Errors
  • Receive and Transmit IP, TCP and UDP Checksum Offload. Both IPv4 and IPv6 Packet Types Supported
  • Address Checking Logic for Four Specific 48-bit Addresses, Four Type IDs, Promiscuous Mode, Hash Matching of Unicast and Multicast Destination Addresses and Wake-on-LAN
  • Management Data Input/Output (MDIO) Interface for Physical Layer Management
  • Support for Jumbo Frames up to 10240 Bytes
  • Full Duplex Flow Control with Recognition of Incoming Pause Frames and Hardware Generation of Transmitted Pause Frames
  • Half Duplex Flow Control by Forcing Collisions on Incoming Frames
  • Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and Priority Tagged Frames
  • Support for 802.1Qbb Priority-based Flow Control
  • Programmable Inter Packet Gap (IPG) Stretch
  • Recognition of IEEE 1588 PTP Frames
  • IEEE 1588 Timestamp Unit (TSU)
  • Support for 802.1AS Timing and Synchronization