The schematic below is given for LPDDR2 but it is also valid for LPDDR3.Figure 34-7. 2x16-bit LPDDR2 Hardware Configuration
CAx LPDDR2/LPDDR3 signals are to be connected as indicated in the table below.
Table 34-3. CAx LPDDR2 Signal Connection
DDR Controller Signal
LPDDR2 Signal
RAS
CA0
CAS
CA1
WE
CA2
DDR_A0
CA3
DDR_A1
CA4
DDR_A2
CA5
DDR_A3
CA6
DDR_A4
CA7
DDR_A5
CA8
DDR_A6
CA9
Higher addresses
Higher CAs
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