22.5.3 Watchdog Timer Status Register
Name: | WDT_SR |
Offset: | 0x08 |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
WDERR | WDUNF | ||||||||
Access | R | R | |||||||
Reset | 0 | 0 |
Bit 1 – WDERR Watchdog Error (cleared on read)
Value | Description |
---|---|
0 | No watchdog error occurred since the last read of WDT_SR. |
1 | At least one watchdog error occurred since the last read of WDT_SR. |
Bit 0 – WDUNF Watchdog Underflow (cleared on read)
Value | Description |
---|---|
0 | No watchdog underflow occurred since the last read of WDT_SR. |
1 | At least one watchdog underflow occurred since the last read of WDT_SR. |