47.6.5 UART Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

Name: UART_IMR
Offset: 0x10
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 CMP     TXEMPTYTIMEOUT 
Access RRR 
Reset 000 
Bit 76543210 
 PAREFRAMEOVRE   TXRDYRXRDY 
Access RRRRR 
Reset 00000 

Bit 15 – CMP Mask Comparison Interrupt

Bit 9 – TXEMPTY Mask TXEMPTY Interrupt

Bit 8 – TIMEOUT Mask Time-out Interrupt

Bit 7 – PARE Mask Parity Error Interrupt

Bit 6 – FRAME Mask Framing Error Interrupt

Bit 5 – OVRE Mask Overrun Error Interrupt

Bit 1 – TXRDY Mask TXRDY Interrupt

Bit 0 – RXRDY Mask RXRDY Interrupt