46.10.65 TWI Clock Waveform Generator Register

FLEX_TWI_CWGR is only used in Host mode.

Name:	FLEX_TWI_CWGR
Offset:	0x610
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
				HOLD[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
				BRSRCCLK		CKDIV[2:0]
Access				R/W		R/W	R/W	R/W
Reset				0		0	0	0


Bit	15	14	13	12	11	10	9	8
	CHDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CLDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 28:24 – HOLD[4:0] TWD Hold Time Versus TWCK Falling

If High-speed mode is selected TWD is internally modified on the TWCK falling edge to meet the I2C specified maximum hold time, else if High-speed mode is not configured TWD is kept unchanged after TWCK falling edge for a period of (HOLD + 3) × t_{peripheral clock}.

Bit 20 – BRSRCCLK Bit Rate Source Clock

Value	Name	Description
0	PERIPH_CLK	The peripheral clock is the source clock for the bit rate generation.
1	GCLK	GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock.

Bits 18:16 – CKDIV[2:0] Clock Divider

The CKDIV is used to increase both SCL high and low periods.

Bits 15:8 – CHDIV[7:0] Clock High Divider

The SCL high period is defined as follows:

If FLEX_TWI_FILTR.FILT = 0

If BRSRCCLK = 0: CHDIV = ((t_high/t_{peripheral clock}) - 3)/2^CKDIV
If BRSRCCLK = 1: CHDIV = (t_high/t_{ext_ck})/2^CKDIV

If FLEX_TWI_FILTR.FILT = 1

If BRSRCCLK = 0: CHDIV = ((t_high/t_{peripheral clock}) - 3 - (THRES+1))/2^CKDIV
If BRSRCCLK = 1: CHDIV = ((t_high - (THRES+1) * t_{peripheral
clock})/t_{ext_ck})/2^CKDIV

Bits 7:0 – CLDIV[7:0] Clock Low Divider

The SCL low period is defined as follows: