46.10.65 TWI Clock Waveform Generator Register

FLEX_TWI_CWGR is only used in Host mode.

Name: FLEX_TWI_CWGR
Offset: 0x610
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
    HOLD[4:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 2322212019181716 
    BRSRCCLK CKDIV[2:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
 CHDIV[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 CLDIV[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 28:24 – HOLD[4:0] TWD Hold Time Versus TWCK Falling

If High-speed mode is selected TWD is internally modified on the TWCK falling edge to meet the I2C specified maximum hold time, else if High-speed mode is not configured TWD is kept unchanged after TWCK falling edge for a period of (HOLD + 3) × tperipheral clock.

Bit 20 – BRSRCCLK Bit Rate Source Clock

ValueNameDescription
0 PERIPH_CLK

The peripheral clock is the source clock for the bit rate generation.

1 GCLK

GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock.

Bits 18:16 – CKDIV[2:0] Clock Divider

The CKDIV is used to increase both SCL high and low periods.

Bits 15:8 – CHDIV[7:0] Clock High Divider

The SCL high period is defined as follows:

If FLEX_TWI_FILTR.FILT = 0

  • If BRSRCCLK = 0: CHDIV = ((thigh/tperipheral clock) - 3)/2CKDIV
  • If BRSRCCLK = 1: CHDIV = (thigh/text_ck)/2CKDIV

If FLEX_TWI_FILTR.FILT = 1

  • If BRSRCCLK = 0: CHDIV = ((thigh/tperipheral clock) - 3 - (THRES+1))/2CKDIV
  • If BRSRCCLK = 1: CHDIV = ((thigh - (THRES+1) * tperipheral clock)/text_ck)/2CKDIV

Bits 7:0 – CLDIV[7:0] Clock Low Divider

The SCL low period is defined as follows:

If FLEX_TWI_FILTR.FILT = 0

  • If BRSRCCLK = 0: CLDIV = ((tlow/tperipheral clock) - 3)/2CKDIV
  • If BRSRCCLK = 1: CLDIV = (tlow/text_ck)/2CKDIV

If FLEX_TWI_FILTR.FILT = 1

  • If BRSRCCLK = 0: CLDIV = ((tlow/tperipheral clock) - 3 - (THRES+1))/2CKDIV
  • If BRSRCCLK = 1: CLDIV = ((tlow - (THRES+1) * tperipheral clock)/text_ck)/2CKDIV