35.7 Register Summary
The User Interface is connected to the APB bus. The MPDDRC is programmed using the registers listed in the following table.
Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|
0x00 | MPDDRC_MR | 31:24 | ||||||||
23:16 | ||||||||||
15:8 | MRS[7:0] | |||||||||
7:0 | DAI | MODE[2:0] | ||||||||
0x04 | MPDDRC_RTR | 31:24 | ||||||||
23:16 | MR4_VALUE[2:0] | REF_PB | ADJ_REF | |||||||
15:8 | COUNT[11:8] | |||||||||
7:0 | COUNT[7:0] | |||||||||
0x08 | MPDDRC_CR | 31:24 | ||||||||
23:16 | UNAL | DECOD | NDQS | NB | LC_LPDDR1 | ENRDM | DQMS | |||
15:8 | OCD[2:0] | ZQ[1:0] | DIS_DLL | DIC_DS | ||||||
7:0 | DLL | CAS[2:0] | NR[1:0] | NC[1:0] | ||||||
0x0C | MPDDRC_TPR0 | 31:24 | TMRD[3:0] | TWTR[2:0] | ||||||
23:16 | TRRD[3:0] | TRP[3:0] | ||||||||
15:8 | TRC[3:0] | TWR[3:0] | ||||||||
7:0 | TRCD[3:0] | TRAS[3:0] | ||||||||
0x10 | MPDDRC_TPR1 | 31:24 | TXP[3:0] | |||||||
23:16 | TXSRD[7:0] | |||||||||
15:8 | TXSNR[7:0] | |||||||||
7:0 | TRFC[6:0] | |||||||||
0x14 | MPDDRC_TPR2 | 31:24 | ||||||||
23:16 | TFAW[3:0] | |||||||||
15:8 | TRTP[2:0] | TRPA[3:0] | ||||||||
7:0 | TXARDS[3:0] | TXARD[3:0] | ||||||||
0x18 ... 0x1B | Reserved | |||||||||
0x1C | MPDDRC_LPR | 31:24 | SELF_DONE | CHG_FRQ | ||||||
23:16 | UPD_MR[1:0] | APDE | ||||||||
15:8 | TIMEOUT[1:0] | DS[2:0] | ||||||||
7:0 | PASR[2:0] | LPDDR2_LPDDR3_PWOFF | CLK_FR | LPCB[1:0] | ||||||
0x20 | MPDDRC_MD | 31:24 | IO_WIDTH[1:0] | DENSITY[3:0] | TYPE[1:0] | |||||
23:16 | REV_ID[7:0] | |||||||||
15:8 | MANU_ID[7:0] | |||||||||
7:0 | RL3 | WL | DBW | MD[2:0] | ||||||
0x24 ... 0x27 | Reserved | |||||||||
0x28 | MPDDRC_LPDDR23_LPR | 31:24 | DS[3:0] | |||||||
23:16 | SEG_MASK[15:8] | |||||||||
15:8 | SEG_MASK[7:0] | |||||||||
7:0 | BK_MASK_PASR[7:0] | |||||||||
0x2C | MPDDRC_LPDDR2_LPDDR3_DDR3_CAL_MR4 | 31:24 | MR4_READ[15:8] | |||||||
23:16 | MR4_READ[7:0] | |||||||||
15:8 | COUNT_CAL[15:8] | |||||||||
7:0 | COUNT_CAL[7:0] | |||||||||
0x30 | MPDDRC_LPDDR2_LPDDR3_DDR3_TIM_CAL | 31:24 | ||||||||
23:16 | RZQI[1:0] | |||||||||
15:8 | ||||||||||
7:0 | ZQCS[7:0] | |||||||||
0x34 | MPDDRC_IO_CALIBR | 31:24 | ||||||||
23:16 | CALCODEN[3:0] | CALCODEP[3:0] | ||||||||
15:8 | TZQIO[6:0] | |||||||||
7:0 | EN_CALIB | RDIV[2:0] | ||||||||
0x38 | MPDDRC_OCMS | 31:24 | ||||||||
23:16 | ||||||||||
15:8 | ||||||||||
7:0 | SCR_EN | |||||||||
0x3C | MPDDRC_OCMS_KEY1 | 31:24 | KEY1[31:24] | |||||||
23:16 | KEY1[23:16] | |||||||||
15:8 | KEY1[15:8] | |||||||||
7:0 | KEY1[7:0] | |||||||||
0x40 | MPDDRC_OCMS_KEY2 | 31:24 | KEY2[31:24] | |||||||
23:16 | KEY2[23:16] | |||||||||
15:8 | KEY2[15:8] | |||||||||
7:0 | KEY2[7:0] | |||||||||
0x44 | MPDDRC_CONF_ARBITER | 31:24 | BDW_BURST_P7 | BDW_BURST_P6 | BDW_BURST_P5 | BDW_BURST_P4 | BDW_BURST_P3 | BDW_BURST_P2 | BDW_BURST_P1 | BDW_BURST_P0 |
23:16 | MA_PR_P7 | MA_PR_P6 | MA_PR_P5 | MA_PR_P4 | MA_PR_P3 | MA_PR_P2 | MA_PR_P1 | MA_PR_P0 | ||
15:8 | RQ_WD_P7 | RQ_WD_P6 | RQ_WD_P5 | RQ_WD_P4 | RQ_WD_P3 | RQ_WD_P2 | RQ_WD_P1 | RQ_WD_P0 | ||
7:0 | BDW_MAX_CUR | ARB[1:0] | ||||||||
0x48 | MPDDRC_TIMEOUT | 31:24 | TIMEOUT_P7[3:0] | TIMEOUT_P6[3:0] | ||||||
23:16 | TIMEOUT_P5[3:0] | TIMEOUT_P4[3:0] | ||||||||
15:8 | TIMEOUT_P3[3:0] | TIMEOUT_P2[3:0] | ||||||||
7:0 | TIMEOUT_P1[3:0] | TIMEOUT_P0[3:0] | ||||||||
0x4C | MPDDRC_REQ_PORT_0123 | 31:24 | NRQ_NWD_BDW_P3[7:0] | |||||||
23:16 | NRQ_NWD_BDW_P2[7:0] | |||||||||
15:8 | NRQ_NWD_BDW_P1[7:0] | |||||||||
7:0 | NRQ_NWD_BDW_P0[7:0] | |||||||||
0x50 | MPDDRC_REQ_PORT_4567 | 31:24 | NRQ_NWD_BDW_P7[7:0] | |||||||
23:16 | NRQ_NWD_BDW_P6[7:0] | |||||||||
15:8 | NRQ_NWD_BDW_P5[7:0] | |||||||||
7:0 | NRQ_NWD_BDW_P4[7:0] | |||||||||
0x54 | MPDDRC_BDW_PORT_0123 | 31:24 | BDW_P3[6:0] | |||||||
23:16 | BDW_P2[6:0] | |||||||||
15:8 | BDW_P1[6:0] | |||||||||
7:0 | BDW_P0[6:0] | |||||||||
0x58 | MPDDRC_BDW_PORT_4567 | 31:24 | BDW_P7[7:0] | |||||||
23:16 | BDW_P6[7:0] | |||||||||
15:8 | BDW_P5[7:0] | |||||||||
7:0 | BDW_P4[7:0] | |||||||||
0x5C | MPDDRC_RD_DATA_PATH | 31:24 | ||||||||
23:16 | ||||||||||
15:8 | ||||||||||
7:0 | SHIFT_SAMPLING[1:0] | |||||||||
0x60 | MPDDRC_MCFGR | 31:24 | ||||||||
23:16 | ||||||||||
15:8 | INFO[1:0] | REFR_CALIB | READ_WRITE[1:0] | |||||||
7:0 | RUN | SOFT_RESET | EN_MONI | |||||||
0x64 | MPDDRC_MADDR0 | 31:24 | ADDR_HIGH_PORT0[15:8] | |||||||
23:16 | ADDR_HIGH_PORT0[7:0] | |||||||||
15:8 | ADDR_LOW_PORT0[15:8] | |||||||||
7:0 | ADDR_LOW_PORT0[7:0] | |||||||||
0x68 | MPDDRC_MADDR1 | 31:24 | ADDR_HIGH_PORT1[15:8] | |||||||
23:16 | ADDR_HIGH_PORT1[7:0] | |||||||||
15:8 | ADDR_LOW_PORT1[15:8] | |||||||||
7:0 | ADDR_LOW_PORT1[7:0] | |||||||||
0x6C | MPDDRC_MADDR2 | 31:24 | ADDR_HIGH_PORT2[15:8] | |||||||
23:16 | ADDR_HIGH_PORT2[7:0] | |||||||||
15:8 | ADDR_LOW_PORT2[15:8] | |||||||||
7:0 | ADDR_LOW_PORT2[7:0] | |||||||||
0x70 | MPDDRC_MADDR3 | 31:24 | ADDR_HIGH_PORT3[15:8] | |||||||
23:16 | ADDR_HIGH_PORT3[7:0] | |||||||||
15:8 | ADDR_LOW_PORT3[15:8] | |||||||||
7:0 | ADDR_LOW_PORT3[7:0] | |||||||||
0x74 | MPDDRC_MADDR4 | 31:24 | ADDR_HIGH_PORT4[15:8] | |||||||
23:16 | ADDR_HIGH_PORT4[7:0] | |||||||||
15:8 | ADDR_LOW_PORT4[15:8] | |||||||||
7:0 | ADDR_LOW_PORT4[7:0] | |||||||||
0x78 | MPDDRC_MADDR5 | 31:24 | ADDR_HIGH_PORT5[15:8] | |||||||
23:16 | ADDR_HIGH_PORT5[7:0] | |||||||||
15:8 | ADDR_LOW_PORT5[15:8] | |||||||||
7:0 | ADDR_LOW_PORT5[7:0] | |||||||||
0x7C | MPDDRC_MADDR6 | 31:24 | ADDR_HIGH_PORT6[15:8] | |||||||
23:16 | ADDR_HIGH_PORT6[7:0] | |||||||||
15:8 | ADDR_LOW_PORT6[15:8] | |||||||||
7:0 | ADDR_LOW_PORT6[7:0] | |||||||||
0x80 | MPDDRC_MADDR7 | 31:24 | ADDR_HIGH_PORT7[15:8] | |||||||
23:16 | ADDR_HIGH_PORT7[7:0] | |||||||||
15:8 | ADDR_LOW_PORT7[15:8] | |||||||||
7:0 | ADDR_LOW_PORT7[7:0] | |||||||||
0x84 | MPDDRC_MINFO0 (MAX_WAIT) | 31:24 | READ_WRITE | |||||||
23:16 | SIZE[2:0] | BURST[2:0] | ||||||||
15:8 | MAX_PORT0_WAITING[15:8] | |||||||||
7:0 | MAX_PORT0_WAITING[7:0] | |||||||||
0x84 | MPDDRC_MINFO0 (NB_TRANSFERS) | 31:24 | P0_NB_TRANSFERS[31:24] | |||||||
23:16 | P0_NB_TRANSFERS[23:16] | |||||||||
15:8 | P0_NB_TRANSFERS[15:8] | |||||||||
7:0 | P0_NB_TRANSFERS[7:0] | |||||||||
0x84 | MPDDRC_MINFO0 (TOTAL_LATENCY) | 31:24 | P0_TOTAL_LATENCY[31:24] | |||||||
23:16 | P0_TOTAL_LATENCY[23:16] | |||||||||
15:8 | P0_TOTAL_LATENCY[15:8] | |||||||||
7:0 | P0_TOTAL_LATENCY[7:0] | |||||||||
0x88 | MPDDRC_MINFO1 (MAX_WAIT) | 31:24 | READ_WRITE | |||||||
23:16 | SIZE[2:0] | BURST[2:0] | ||||||||
15:8 | MAX_PORT1_WAITING[15:8] | |||||||||
7:0 | MAX_PORT1_WAITING[7:0] | |||||||||
0x88 | MPDDRC_MINFO1 (NB_TRANSFERS) | 31:24 | P1_NB_TRANSFERS[31:24] | |||||||
23:16 | P1_NB_TRANSFERS[23:16] | |||||||||
15:8 | P1_NB_TRANSFERS[15:8] | |||||||||
7:0 | P1_NB_TRANSFERS[7:0] | |||||||||
0x88 | MPDDRC_MINFO1 (TOTAL_LATENCY) | 31:24 | P1_TOTAL_LATENCY[31:24] | |||||||
23:16 | P1_TOTAL_LATENCY[23:16] | |||||||||
15:8 | P1_TOTAL_LATENCY[15:8] | |||||||||
7:0 | P1_TOTAL_LATENCY[7:0] | |||||||||
0x8C | MPDDRC_MINFO2 (MAX_WAIT) | 31:24 | READ_WRITE | |||||||
23:16 | SIZE[2:0] | BURST[2:0] | ||||||||
15:8 | MAX_PORT2_WAITING[15:8] | |||||||||
7:0 | MAX_PORT2_WAITING[7:0] | |||||||||
0x8C | MPDDRC_MINFO2 (NB_TRANSFERS) | 31:24 | P2_NB_TRANSFERS[31:24] | |||||||
23:16 | P2_NB_TRANSFERS[23:16] | |||||||||
15:8 | P2_NB_TRANSFERS[15:8] | |||||||||
7:0 | P2_NB_TRANSFERS[7:0] | |||||||||
0x8C | MPDDRC_MINFO2 (TOTAL_LATENCY) | 31:24 | P2_TOTAL_LATENCY[31:24] | |||||||
23:16 | P2_TOTAL_LATENCY[23:16] | |||||||||
15:8 | P2_TOTAL_LATENCY[15:8] | |||||||||
7:0 | P2_TOTAL_LATENCY[7:0] | |||||||||
0x90 | MPDDRC_MINFO3 (MAX_WAIT) | 31:24 | READ_WRITE | |||||||
23:16 | SIZE[2:0] | BURST[2:0] | ||||||||
15:8 | MAX_PORT3_WAITING[15:8] | |||||||||
7:0 | MAX_PORT3_WAITING[7:0] | |||||||||
0x90 | MPDDRC_MINFO3 (NB_TRANSFERS) | 31:24 | P3_NB_TRANSFERS[31:24] | |||||||
23:16 | P3_NB_TRANSFERS[23:16] | |||||||||
15:8 | P3_NB_TRANSFERS[15:8] | |||||||||
7:0 | P3_NB_TRANSFERS[7:0] | |||||||||
0x90 | MPDDRC_MINFO3 (TOTAL_LATENCY) | 31:24 | P3_TOTAL_LATENCY[31:24] | |||||||
23:16 | P3_TOTAL_LATENCY[23:16] | |||||||||
15:8 | P3_TOTAL_LATENCY[15:8] | |||||||||
7:0 | P3_TOTAL_LATENCY[7:0] | |||||||||
0x94 | MPDDRC_MINFO4 (MAX_WAIT) | 31:24 | READ_WRITE | |||||||
23:16 | SIZE[2:0] | BURST[2:0] | ||||||||
15:8 | MAX_PORT4_WAITING[15:8] | |||||||||
7:0 | MAX_PORT4_WAITING[7:0] | |||||||||
0x94 | MPDDRC_MINFO4 (NB_TRANSFERS) | 31:24 | P4_NB_TRANSFERS[31:24] | |||||||
23:16 | P4_NB_TRANSFERS[23:16] | |||||||||
15:8 | P4_NB_TRANSFERS[15:8] | |||||||||
7:0 | P4_NB_TRANSFERS[7:0] | |||||||||
0x94 | MPDDRC_MINFO4 (TOTAL_LATENCY) | 31:24 | P4_TOTAL_LATENCY[31:24] | |||||||
23:16 | P4_TOTAL_LATENCY[23:16] | |||||||||
15:8 | P4_TOTAL_LATENCY[15:8] | |||||||||
7:0 | P4_TOTAL_LATENCY[7:0] | |||||||||
0x98 | MPDDRC_MINFO5 (MAX_WAIT) | 31:24 | READ_WRITE | |||||||
23:16 | SIZE[2:0] | BURST[2:0] | ||||||||
15:8 | MAX_PORT5_WAITING[15:8] | |||||||||
7:0 | MAX_PORT5_WAITING[7:0] | |||||||||
0x98 | MPDDRC_MINFO5 (NB_TRANSFERS) | 31:24 | P5_NB_TRANSFERS[31:24] | |||||||
23:16 | P5_NB_TRANSFERS[23:16] | |||||||||
15:8 | P5_NB_TRANSFERS[15:8] | |||||||||
7:0 | P5_NB_TRANSFERS[7:0] | |||||||||
0x98 | MPDDRC_MINFO5 (TOTAL_LATENCY) | 31:24 | P5_TOTAL_LATENCY[31:24] | |||||||
23:16 | P5_TOTAL_LATENCY[23:16] | |||||||||
15:8 | P5_TOTAL_LATENCY[15:8] | |||||||||
7:0 | P5_TOTAL_LATENCY[7:0] | |||||||||
0x9C | MPDDRC_MINFO6 (MAX_WAIT) | 31:24 | READ_WRITE | |||||||
23:16 | SIZE[2:0] | BURST[2:0] | ||||||||
15:8 | MAX_PORT6_WAITING[15:8] | |||||||||
7:0 | MAX_PORT6_WAITING[7:0] | |||||||||
0x9C | MPDDRC_MINFO6 (NB_TRANSFERS) | 31:24 | P6_NB_TRANSFERS[31:24] | |||||||
23:16 | P6_NB_TRANSFERS[23:16] | |||||||||
15:8 | P6_NB_TRANSFERS[15:8] | |||||||||
7:0 | P6_NB_TRANSFERS[7:0] | |||||||||
0x9C | MPDDRC_MINFO6 (TOTAL_LATENCY) | 31:24 | P6_TOTAL_LATENCY[31:24] | |||||||
23:16 | P6_TOTAL_LATENCY[23:16] | |||||||||
15:8 | P6_TOTAL_LATENCY[15:8] | |||||||||
7:0 | P6_TOTAL_LATENCY[7:0] | |||||||||
0xA0 | MPDDRC_MINFO7 (MAX_WAIT) | 31:24 | READ_WRITE | |||||||
23:16 | SIZE[2:0] | BURST[2:0] | ||||||||
15:8 | MAX_PORT7_WAITING[15:8] | |||||||||
7:0 | MAX_PORT7_WAITING[7:0] | |||||||||
0xA0 | MPDDRC_MINFO7 (NB_TRANSFERS) | 31:24 | P7_NB_TRANSFERS[31:24] | |||||||
23:16 | P7_NB_TRANSFERS[23:16] | |||||||||
15:8 | P7_NB_TRANSFERS[15:8] | |||||||||
7:0 | P7_NB_TRANSFERS[7:0] | |||||||||
0xA0 | MPDDRC_MINFO7 (TOTAL_LATENCY) | 31:24 | P7_TOTAL_LATENCY[31:24] | |||||||
23:16 | P7_TOTAL_LATENCY[23:16] | |||||||||
15:8 | P7_TOTAL_LATENCY[15:8] | |||||||||
7:0 | P7_TOTAL_LATENCY[7:0] | |||||||||
0xA4 ... 0xE3 | Reserved | |||||||||
0xE4 | MPDDRC_WPMR | 31:24 | WPKEY[23:16] | |||||||
23:16 | WPKEY[15:8] | |||||||||
15:8 | WPKEY[7:0] | |||||||||
7:0 | WPEN | |||||||||
0xE8 | MPDDRC_WPSR | 31:24 | ||||||||
23:16 | WPVSRC[15:8] | |||||||||
15:8 | WPVSRC[7:0] | |||||||||
7:0 | WPVS |