46.10.48 SPI Transmit Data Register

If FIFO is enabled (FLEX_SPI_CR.FIFOEN=1), a byte/halfword access on FLEX_SPI_TDR writes one byte/halfword, see SPI Single Data Access for details.

Name: FLEX_SPI_TDR
Offset: 0x40C
Reset: 
Property: Write-only

Bit 3130292827262524 
        LASTXFER 
Access W 
Reset  
Bit 2322212019181716 
     PCS[3:0] 
Access WWWW 
Reset  
Bit 15141312111098 
 TD[15:8] 
Access WWWWWWWW 
Reset  
Bit 76543210 
 TD[7:0] 
Access WWWWWWWW 
Reset  

Bit 24 – LASTXFER Last Transfer

This field is only used if variable peripheral select is active (FLEX_SPI_MR.PS = 1).

ValueDescription
0

No effect.

1

The current NPCS is de-asserted after the transfer of the character written in TD. When FLEX_SPI_CSRx.CSAAT is set, the communication with the current serial peripheral can be closed by raising the corresponding NPCS line as soon as TD transfer is completed.

Bits 19:16 – PCS[3:0] Peripheral Chip Select

This field is only used if variable peripheral select is active (FLEX_SPI_MR.PS = 1).

If FLEX_SPI_MR.PCSDEC = 0:

PCS = x0 NPCS[1:0] = 10

PCS = 01 NPCS[1:0] = 01

PCS = 11 forbidden (no peripheral is selected)

(x = don’t care)

If FLEX_SPI_MR.PCSDEC = 1:

NPCS[1:0] output signals = PCS

Bits 15:0 – TD[15:0] Transmit Data

Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.