18.4.1 Matrix Hosts
The H32MX manages eight hosts, which means that each host can perform an access, concurrently with others, to an available client.
This matrix can operate at MCK if MCK is lower than 83 MHz, or at MCK/2 if MCK is higher than 83 MHz. Refer to the section “Power Management Controller (PMC)” for more details.
Each host has its own decoder, which is defined specifically for each host. In order to simplify the addressing, all the hosts have the same decodings.
| Host No. | Name | Security Type |
|---|---|---|
| 0 | Bridge from H64MX to H32MX | Not applicable |
| 1 | Integrity Check Monitor (ICM) | Peripheral Securable |
| 2 | UHPHS EHCI DMA | Peripheral Securable |
| 3 | UHPHS OHCI DMA | Peripheral Securable |
| 4 | UDPHS DMA | Peripheral Securable |
| 5 | GMAC DMA | Peripheral Securable |
| 6 | CAN0 DMA | Peripheral Securable |
| 7 | CAN1 DMA | Peripheral Securable |