38.6 Functional Description

The LCD module integrates the following digital blocks:

• DMA Engine Address Generation (DEAG)—this block performs data prefetch and requests access to the system bus interface.
• Input Overlay FIFO—stores the stream of pixels
• Color Lookup Table (CLUT)—these 256 RAM-based lookup table entries are selected when the color depth is set to 1, 2, 4 or 8 bpp.
• Chroma Upsampling Engine (CUE)—this block is selected when the input image sampling format is YUV (Y’CbCr) 4:2:0 and converts it to higher quality 4:4:4 image.
• Color Space Conversion (CSC)—changes the color space from YUV to RGB
• Two Dimension Scaler (2DSC)—resizes the image
• Global Alpha Blender (GAB)—performs programmable 256-level alpha blending
• Output FIFO—stores the blended pixel prior to display
• LCD Timing Engine—provides a fully programmable HSYNC-VSYNC interface

The DMA controller reads the image through the system bus host interface. The LCD controller engine formats the display data, then the GAB performs alpha blending if required, and writes the final pixel into the output FIFO. The programmable timing engine drives a valid pixel onto the LCDDAT[23:0] display bus.