36.20.40 Off Chip Memory Scrambling Key2 Register
Name: | HSMC_KEY2 |
Offset: | 0x7A8 |
Reset: | 0x00000000 |
Property: | Write-once |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
KEY2[31:24] | |||||||||
Access | W-once | W-once | W-once | W-once | W-once | W-once | W-once | W-once | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
KEY2[23:16] | |||||||||
Access | W-once | W-once | W-once | W-once | W-once | W-once | W-once | W-once | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
KEY2[15:8] | |||||||||
Access | W-once | W-once | W-once | W-once | W-once | W-once | W-once | W-once | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
KEY2[7:0] | |||||||||
Access | W-once | W-once | W-once | W-once | W-once | W-once | W-once | W-once | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:0 – KEY2[31:0] Off Chip Memory Scrambling (OCMS) Key Part 2
When Off Chip Memory Scrambling is enabled by setting the HSMC_OCMS and HSMC_TIMINGS registers in accordance, the data scrambling depends on KEY2 and KEY1 values.