48.8.14 SPI FIFO Level Register
Name: | SPI_FLR |
Offset: | 0x44 |
Reset: | 0x0 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
RXFL[5:0] | |||||||||
Access | R | R | R | R | R | R | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TXFL[5:0] | |||||||||
Access | R | R | R | R | R | R | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 21:16 – RXFL[5:0] Receive FIFO Level
Value | Description |
---|---|
0 |
There is no unread data in the Receive FIFO. |
1–16 |
Indicates the number of unread data in the Receive FIFO. |
Bits 5:0 – TXFL[5:0] Transmit FIFO Level
Value | Description |
---|---|
0 |
There is no data in the Transmit FIFO. |
1–16 |
Indicates the number of data in the Transmit FIFO. |