36.20.39 Off Chip Memory Scrambling Key1 Register
Name: | HSMC_KEY1 |
Offset: | 0x7A4 |
Reset: | 0x00000000 |
Property: | Write-once |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
KEY1[31:24] | |||||||||
Access | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
KEY1[23:16] | |||||||||
Access | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
KEY1[15:8] | |||||||||
Access | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
KEY1[7:0] | |||||||||
Access | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | W-Once | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:0 – KEY1[31:0] Off Chip Memory Scrambling (OCMS) Key Part 1
When Off Chip Memory Scrambling is enabled by setting the HSMC_OCMS and HSMC_TIMINGS registers in accordance, the data scrambling depends on KEY1 and KEY2 values.