46.10.79 TWI FIFO Mode Register

This register reads ‘0’ if the FIFO is disabled (see FLEX_TWI_CR to enable/disable the internal FIFO).

This register can only be written if the WPEN bit is cleared in the TWI Write Protection Mode Register.

Name: FLEX_TWI_FMR
Offset: 0x650
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
   RXFTHRES[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
   TXFTHRES[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   RXRDYM[1:0]  TXRDYM[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 29:24 – RXFTHRES[5:0] Receive FIFO Threshold

ValueDescription
0–16 Defines the Receive FIFO threshold value (number of bytes). The FLEX_TWI_FSR.RXFTH flag will be set when Receive FIFO goes from “below” threshold state to “equal to or above” threshold state.

Bits 21:16 – TXFTHRES[5:0] Transmit FIFO Threshold

ValueDescription
0–16 Defines the Transmit FIFO threshold value (number of bytes). The FLEX_TWI_FSR.TXFTH flag will be set when Transmit FIFO goes from “above” threshold state to “equal to or below” threshold state.

Bits 5:4 – RXRDYM[1:0] Receiver Ready Mode

If FIFOs are enabled, the FLEX_TWI_SR.RXRDY flag behaves as follows.

ValueNameDescription
0 ONE_DATA

RXRDY will be at level ‘1’ when at least one unread data is in the receive FIFO.

When DMA is enabled to transfer data the chunk of 1 byte must be configured in the DMA.

If the transfer is performed by software, the access type (byte, halfword) must be defined accordingly.

1 TWO_DATA

RXRDY will be at level ‘1’ when at least two unread data are in the receive FIFO.

To minimize system bus load, when DMA is enabled to transfer data, the chunk of 1 halfword (1 halfword carries 2 bytes) must be configured in the DMA.

If the transfer is performed by software, the access type can be defined as byte (1 byte per access, 2 accesses) or halfword (2 bytes per access, 1 single access).

2 FOUR_DATA

RXRDY will be at level ‘1’ when at least four unread data are in the receive FIFO.

To minimize system bus load, when DMA is enabled to transfer data, the chunk of 1 word (1 word carries 4 bytes) must be configured in the DMA.

If the transfer is performed by software, the access type can be defined as byte (1 byte per access, 4 accesses), halfword (2 bytes per access, 2 accesses) or word (4 bytes per access, 1 single access).

Bits 1:0 – TXRDYM[1:0] Transmitter Ready Mode

If FIFOs are enabled, the FLEX_TWI_SR.TXRDY flag behaves as follows.

ValueNameDescription
0 ONE_DATA

TXRDY will be at level ‘1’ when at least one data can be written in the transmit FIFO.

When DMA is enabled to transfer data, the chunk of 1 byte must be configured in the DMA.

If the transfer is performed by software, the access type must be defined as byte.

1 TWO_DATA

TXRDY will be at level ‘1’ when at least two data can be written in the transmit FIFO.

To minimize system bus load, when DMA is enabled to transfer data, the chunk of 1 halfword (1 halfword carries 2 bytes) must be configured in the DMA.

If the transfer is performed by software, the access type can be defined as byte (1 byte per access, 2 accesses) or halfword (2 bytes per access, 1 single access).

2 FOUR_DATA

TXRDY will be at level ‘1’ when at least four data can be written in the transmit FIFO.

To minimize system bus load, when DMA is enabled to transfer data, the chunk of 1 word (1 word carries 4 bytes) must be configured in the DMA.

If the transfer is performed by software, the access type can be defined as byte (1 byte per access, 4 accesses), halfword (2 bytes per access, 2 accesses) or word (4 bytes per access, 1 single access).