SAMA5D2 Series

66.18.3 LPDDR1-SDRAM

Note: For LPDDR1 memory, the SHIFT_SAMPLING field value in the MPRDDRC_RD_DATA_PATH register must be configured as follows:

SHIFT_SAMPLING = 0 for 0 < DDR_CLK < 94 MHz

SHIFT_SAMPLING = 1 for 94 MHz < DDR_CLK < 166 MHz

Table 66-78. System Clock Waveform Parameters
Symbol	Parameter	Conditions	Min	Max	Unit
t_DDRCK	DDRCK Cycle Time	VDDCORE[1.1V, 1.32V]	7.5	–	ns
t_DDRCK	DDRCK Cycle Time	VDDCORE[1.2V, 1.32V], VDDIODDR[1.8V, 1.9V]	6	–	ns

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