70.7 Revision DS60001476C

Changes
Global format change In peripheral sections: - User Interface table is now called Register Summary and features new information. - Details for registers have changed. The details are now Name, Offset, Reset and Property ^(Note). - Each bitfield now displays its Access and Reset value. Note: Absolute register addresses are available in Memories.
Updated Block Diagram.
Updated Signal Description List for PTC signals.
Table Pin Description (all packages): added note on JTAG boundary scan.
Memory Mapping
In Figure 8-1, updated SYSCWP, PMC, RTC and RSTC.
Debug and Test Features
Updated Figure 15-2.
Deleted section Chip Access Using JTAG Connection.
Updated Product part number and JTAG ID Code value in Boundary JTAG ID Register.
Updated Product Version Number and Debug Port JTAG IDCODE in JTAG-DP Device ID Code Register.
Standard Boot Strategies
Updated Boot Configuration.
Matrix (H64MX/H32MX)
Updated table Peripheral Identifiers.
Master to Slave Access on H32MX: connection between ICM and H32MX removed.
Added note on AESB after table Master to Slave Access on H64MX.
Section "TrustZone Extension to AHB and APB" renamed to 18.12 TrustZone Technology and reorganized content.
In Principles, renamed ‘Always Non-secure’ to ‘Never Secure’
Special Function Registers (SFR)
Section SFR_OHCIICR19.3.2 OHCI Interrupt Configuration Register: updated SUSPEND_A, SUSPEND_B and SUSPEND_C definitions
Advanced Interrupt Controller (AIC)
Updated Figure 21-8.
Updated Figure in Section 21.3 Block Diagram; updated Section 21.7.3 Interrupt Sources.
Shutdown Controller (SHDWC)
Added information on Write Protection.
Periodic Interval Timer (PIT)
Added information on Write Protection.
Real-time Clock (RTC)
Updated content of section Waveform Generation.
Added information about how to clear bits/fields.
System Controller Write Protection
Section 27.1.2 Register Write Protection: updated list of write-protected registers.
Slow Clock Controller (SCKC)
Updated: Section 28.1 Description Section 28.3 Block Diagram Section 28.4 Functional Description Section 28.4.1 Switching from Embedded Always-on 64 kHz RC Oscillator to 32.768 kHz Crystal Oscillator Section 28.4.2 Switching from 32.768 kHz Crystal Oscillator to Embedded Always-on 64 kHz RC Oscillator Section SCKC_CR
Power Management Controller (PMC)
Clock Assignments: removed LCDC row.
Removed content related to the CKGR_UCKR.BIASEN bit in Section 32.19 Programming Sequence and Section CKGR_UCKR32.22.7 PMC UTMI Clock Configuration Register
Updated Section 32.9 Peripheral and Generic Clock Controller.
Parallel Input/Output Controller (PIO)
Updated Figure 33-2.
External Memories
Table 34-2: Added note on connecting DDR_DQSN.
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Embedded Characteristics: added “Write Leveling not supported” and added “Low-cost LPDDR1with 2 internal banks” and “Arbitration policies” characteristics
Updated Block Diagram.
DDR2-SDRAM Initialization: added Step 2.
Low-power DDR2-SDRAM Initialization: added Step 2.
DDR3-SDRAM/DDR3L-SDRAM Initialization: added Step 2.
Restored title of Refresh (Autorefresh Command).
Scrambling/Unscrambling Function: MPDDRC_KEY1/2 replaced with KEY1/2.
Added Monitor.
Updated Sequential Mapping DDR-SDRAM Configuration Mapping: 8K Rows, 512/1024 Columns, 8 banks and Interleaved Mapping DDR-SDRAM Configuration Mapping: 8K Rows, 512/1024 Columns, 8 banks.
MPDDRC Mode Register: updated DAI bit description.
MPDDRC Configuration Register: updated UNAL bit description.
MPDDRC Memory Device Register: updated WL, RL3, MANU_ID, REV_ID, TYPE, DENSITY and IO_WIDTH bit descriptions.
MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Timing Calibration Register: updated RZQI bit description.
MPDDRC I/O Calibration Register: updated CALCODEP and CALCODEN field descriptions.
MPDDRC Read Data Path Register: updated SHIFT_SAMPLING field description.
MPDDRC Monitor Configuration Register: updated REFR_CALIB bit description.
DMA Controller (XDMAC)
Section 37.5.1 Basic Definitions: added "Stride" definition; added 37.5.2 Data Striding Diagram.
Updated Section 37.8 XDMAC Software Requirements;Section XDMAC_CC37.9.28 XDMAC Channel x Configuration Register [x = 0..15]: updated PROT bit description.
Ethernet MAC (GMAC)
MAC Transmit Block: removed reference to non-existing bit HDFC.
GMAC Network Status Register: updated reset value for GMAC_NSR.
USB High Speed Device Port (UDPHS)
Updated Endpoint Configuration and DPRAM Management.
Removed figure Example of DPRAM Allocation and Reorganization.
USB Host High Speed Port (UHPHS)
Updated Section 41.3 Block Diagram, Section 41.5.1 I/O Lines, Section 41.6.2 EHCI, and Section 41.6.3 OHCI.
Power Management: removed reference to bit BIASEN (UTMI BIAS Enable).
Updated Figure 41-2.
Added Section 41.6.1 UTMI Transceivers Sharing.
Section UHPHS_USBCMD41.4 UHPHS USB Command Register: USBCMD reset value set to 0x00080B00 (instead of "0x00080000 or 0x00080B00").
Section UHPHS_PORTSCx41.11 UHPHS Port Status and Control Register: UHPHS_PORTSCx reset value set to 0x00002000 (instead of "0x00002000 or 0x00003000").
Deleted registers UHPHS_INSNREG00 to UHPHS_INSNREG05.
Two-wire Interface (TWIHS)
Table 45-1: START byte support now available. Updated Note 2.
Replaced sections "Master Mode FIFOs" and "Slave Mode FIFOs" by a single Section “FIFOs”.
Section FIFOs, sub-section Overview, the description for FIFO disable/enable has been changed.
Flexible Serial Communication Controller (FLEXCOM)
Section FLEX_US_MR (SPI_MODE)46.10.7 USART Mode Register (SPI_MODE): restored CHMODE field and updated CHMODE description.
Section 46.7.3.1 Transmitter Operations: updated Figure Transmitter Status
Section FLEX_SPI_FMR46.10.55 SPI FIFO Mode Register: updated RXRDYM field description
Updated 46.7.4.1 ISO7816 Mode Overview
Section 46.7.6 RS485 Mode: updated Figure Example of RTS Drive with Timeguard
TWI Clock Waveform Generator Register: deleted CKSRC description.
Universal Asynchronous Receiver Transmitter (UART)
Section47.3 Block Diagram: RXD/TXD pins were renamed to URXD/UTXD.
Section47.5.7 Register Write Protection: added UART Receiver Time-out Register to the list.
Quad Serial Peripheral Interface (QSPI)
QSPI Bus Clock Modes: updated column “Capture QSCK Edge”.
Secure Digital MultiMedia Card Controller (SDMMC)
SDMMC Preset Value Register: deleted Note from SDMMC_PVRx register description.
SDMMC Maximum Current Capabilities Register: corrected access to Read/Write. Added note on CAPWREN below register table.
SDMMC Capabilities Control Register: updated CAPWREN bit description.
Image Sensor Controller (ISC)
SectionISC_CTRLEN51.7.1 ISC Control Enable Register: added bit FUPPRO at index 9 and bit description.
SectionISC_GAM_CTRL51.7.30 ISC Gamma Correction Control Register: added bit BIPART at index 4 and bit description.
Controller Area Network (MCAN)
Description, Section 52.2 Embedded Characteristics: added information on ISO non-compliance
Pulse Width Modulation Controller (PWM)
PWM Clock Generator: updated figure.
Secure Fuse Controller (SFC)
Number of maskable Data Registers modified to 8. Number of Data Registers modified to 17.
Modified ACE bit name in Section SFC_IER56.5.3 SFC Interrupt Enable Register, Section SFC_IDR56.5.4 SFC Interrupt Disable Register, Section SFC_IMR56.5.5 SFC Interrupt Mask Register and Section SFC_SR56.5.6 SFC Status Register.
Integrity Check Monitor (ICM)
Updated Section 57.5.4.2 Processing Period.
Advanced Encryption Standard (AES)
Section 59.1 Description: added XTS to supported modes.
Section 59.4.2 Operating Modes: added bullet for XTS mode; added bullet for CBC-MAC.
Last Output Data Mode: Added (CBC-MAC) to section title. Added details on CMAC algorithm.
Section59.4.8.1 Manual Mode: table "Authorized Input Data Registers": updated for XTS algorithm.
Section 59.4.8.3 DMA Mode: table "DMA Data Transfer Type for the Different Operating Modes": updated for XTS algorithm.
IPSEC Padding: added detail on padding length.
SSL Padding: added detail on incremental integer values.
Updated DMA Mode.
Updated If AES_MR.LOD = 1.
Triple Data Encryption Standard (TDES)
Last Output Data Mode (CBC-MAC): added “CBC-MAC” in section title and added second paragraph.
Updated Section 61.4.3.3 DMA Mode and Section 61.4.4.2.2 TDES_MR.LOD = 1.
Analog-to-Digital Controller (ADC)
ADC Channel Status Register: updated CHx bit description
Updated USCHx field description in ADC Channel Sequence 1 Register and ADC Channel Sequence 2 Register
Electrical Characteristics
In DC Characteristics updated: - Vhyst parameter - VDDIODDR - conditions for VOL and VOH
Updated Section 66.3.2.2 Backup Mode with DDR in Self-Refresh.
Master Clock Waveform Parameters: changed VDDIODDR range.
Corrected references to CKGR_MOR bits and added VIL_XIN and VIH_XIN parameters in XIN Clock Electrical Characteristics.
Updated 12 MHz RC Oscillator Characteristics.
Updated PLLA Characteristics.
Added ADC Bias Current.
Added Pen Detect Characteristics.
Updated Analog Comparator Characteristics.
Two Wire Serial Bus Requirements: corrected definition of TWCK high and low periods.
DDR2-SDRAM System Clock Waveform Parameters: VDDIODDR range changed.
LPDDR1-SDRAM System Clock Waveform Parameters: VDDIODDR range changed.
Section 66.19 SSC Timings: added SSC14 and SSC15 timings
Schematic Checklist
ICE and JTAG: added note on JTAG boundary scan.
Errata
Removed from data sheet to create separate document, SAMA5D2 Family Silicon Errata and Data Sheet Clarification, document number DS80000803.

Global format change

In peripheral sections:

- User Interface table is now called Register Summary and features new information.

- Details for registers have changed. The details are now Name, Offset, Reset and Property ^(Note).

- Each bitfield now displays its Access and Reset value.

Note: Absolute register addresses are available in Memories.

Updated Block Diagram.

Updated Signal Description List for PTC signals.

Table Pin Description (all packages): added note on JTAG boundary scan.

Memory Mapping

In Figure 8-1, updated SYSCWP, PMC, RTC and RSTC.

Debug and Test Features

Updated Figure 15-2.

Deleted section Chip Access Using JTAG Connection.

Updated Product part number and JTAG ID Code value in Boundary JTAG ID Register.

Updated Product Version Number and Debug Port JTAG IDCODE in JTAG-DP Device ID Code Register.

Standard Boot Strategies

Updated Boot Configuration.

Matrix (H64MX/H32MX)

Updated table Peripheral Identifiers.

Master to Slave Access on H32MX: connection between ICM and H32MX removed.

Added note on AESB after table Master to Slave Access on H64MX.

Section "TrustZone Extension to AHB and APB" renamed to 18.12 TrustZone Technology and reorganized content.

In Principles, renamed ‘Always Non-secure’ to ‘Never Secure’

Special Function Registers (SFR)

Section SFR_OHCIICR19.3.2 OHCI Interrupt Configuration Register: updated SUSPEND_A, SUSPEND_B and SUSPEND_C definitions

Advanced Interrupt Controller (AIC)

Updated Figure 21-8.

Updated Figure in Section 21.3 Block Diagram; updated Section 21.7.3 Interrupt Sources.

Shutdown Controller (SHDWC)

Added information on Write Protection.

Periodic Interval Timer (PIT)

Added information on Write Protection.

Real-time Clock (RTC)

Updated content of section Waveform Generation.

Added information about how to clear bits/fields.

System Controller Write Protection

Section 27.1.2 Register Write Protection: updated list of write-protected registers.

Slow Clock Controller (SCKC)

Updated:

Section 28.1 Description
Section 28.3 Block Diagram
Section 28.4 Functional Description
Section 28.4.1 Switching from Embedded Always-on 64 kHz RC Oscillator to 32.768 kHz Crystal Oscillator
Section 28.4.2 Switching from 32.768 kHz Crystal Oscillator to Embedded Always-on 64 kHz RC Oscillator
Section SCKC_CR

Power Management Controller (PMC)

Clock Assignments: removed LCDC row.

Removed content related to the CKGR_UCKR.BIASEN bit in Section 32.19 Programming Sequence and Section CKGR_UCKR32.22.7 PMC UTMI Clock Configuration Register

Updated Section 32.9 Peripheral and Generic Clock Controller.

Parallel Input/Output Controller (PIO)

Updated Figure 33-2.

External Memories

Table 34-2: Added note on connecting DDR_DQSN.

AHB Multiport DDR-SDRAM Controller (MPDDRC)

Embedded Characteristics: added “Write Leveling not supported” and added “Low-cost LPDDR1with 2 internal banks” and “Arbitration policies” characteristics

Updated Block Diagram.

DDR2-SDRAM Initialization: added Step 2.

Low-power DDR2-SDRAM Initialization: added Step 2.

DDR3-SDRAM/DDR3L-SDRAM Initialization: added Step 2.

Restored title of Refresh (Autorefresh Command).

Scrambling/Unscrambling Function: MPDDRC_KEY1/2 replaced with KEY1/2.

Added Monitor.

Updated Sequential Mapping DDR-SDRAM Configuration Mapping: 8K Rows, 512/1024 Columns, 8 banks and Interleaved Mapping DDR-SDRAM Configuration Mapping: 8K Rows, 512/1024 Columns, 8 banks.

MPDDRC Mode Register: updated DAI bit description.

MPDDRC Configuration Register: updated UNAL bit description.

MPDDRC Memory Device Register: updated WL, RL3, MANU_ID, REV_ID, TYPE, DENSITY and IO_WIDTH bit descriptions.

MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Timing Calibration Register: updated RZQI bit description.

MPDDRC I/O Calibration Register: updated CALCODEP and CALCODEN field descriptions.

MPDDRC Read Data Path Register: updated SHIFT_SAMPLING field description.

MPDDRC Monitor Configuration Register: updated REFR_CALIB bit description.

DMA Controller (XDMAC)

Section 37.5.1 Basic Definitions: added "Stride" definition; added 37.5.2 Data Striding Diagram.

Updated Section 37.8 XDMAC Software Requirements;Section XDMAC_CC37.9.28 XDMAC Channel x Configuration Register [x = 0..15]: updated PROT bit description.

Ethernet MAC (GMAC)

MAC Transmit Block: removed reference to non-existing bit HDFC.

GMAC Network Status Register: updated reset value for GMAC_NSR.

USB High Speed Device Port (UDPHS)

Updated Endpoint Configuration and DPRAM Management.

Removed figure Example of DPRAM Allocation and Reorganization.

USB Host High Speed Port (UHPHS)

Updated Section 41.3 Block Diagram, Section 41.5.1 I/O Lines, Section 41.6.2 EHCI, and Section 41.6.3 OHCI.

Power Management: removed reference to bit BIASEN (UTMI BIAS Enable).

Updated Figure 41-2.

Added Section 41.6.1 UTMI Transceivers Sharing.

Section UHPHS_USBCMD41.4 UHPHS USB Command Register: USBCMD reset value set to 0x00080B00 (instead of "0x00080000 or 0x00080B00").

Section UHPHS_PORTSCx41.11 UHPHS Port Status and Control Register: UHPHS_PORTSCx reset value set to 0x00002000 (instead of "0x00002000 or 0x00003000").

Deleted registers UHPHS_INSNREG00 to UHPHS_INSNREG05.

Two-wire Interface (TWIHS)

Table 45-1: START byte support now available. Updated Note 2.

Replaced sections "Master Mode FIFOs" and "Slave Mode FIFOs" by a single Section “FIFOs”.

Section FIFOs, sub-section Overview, the description for FIFO disable/enable has been changed.

Flexible Serial Communication Controller (FLEXCOM)

Section FLEX_US_MR (SPI_MODE)46.10.7 USART Mode Register (SPI_MODE): restored CHMODE field and updated CHMODE description.

Section 46.7.3.1 Transmitter Operations: updated Figure Transmitter Status

Section FLEX_SPI_FMR46.10.55 SPI FIFO Mode Register: updated RXRDYM field description

Updated 46.7.4.1 ISO7816 Mode Overview

Section 46.7.6 RS485 Mode: updated Figure Example of RTS Drive with Timeguard

TWI Clock Waveform Generator Register: deleted CKSRC description.

Universal Asynchronous Receiver Transmitter (UART)

Section47.3 Block Diagram: RXD/TXD pins were renamed to URXD/UTXD.

Section47.5.7 Register Write Protection: added UART Receiver Time-out Register to the list.

Quad Serial Peripheral Interface (QSPI)

QSPI Bus Clock Modes: updated column “Capture QSCK Edge”.

Secure Digital MultiMedia Card Controller (SDMMC)

SDMMC Preset Value Register: deleted Note from SDMMC_PVRx register description.

SDMMC Maximum Current Capabilities Register: corrected access to Read/Write. Added note on CAPWREN below register table.

SDMMC Capabilities Control Register: updated CAPWREN bit description.

Image Sensor Controller (ISC)

SectionISC_CTRLEN51.7.1 ISC Control Enable Register: added bit FUPPRO at index 9 and bit description.

SectionISC_GAM_CTRL51.7.30 ISC Gamma Correction Control Register: added bit BIPART at index 4 and bit description.

Controller Area Network (MCAN)

Description, Section 52.2 Embedded Characteristics: added information on ISO non-compliance

Pulse Width Modulation Controller (PWM)

PWM Clock Generator: updated figure.

Secure Fuse Controller (SFC)

Number of maskable Data Registers modified to 8. Number of Data Registers modified to 17.

Modified ACE bit name in Section SFC_IER56.5.3 SFC Interrupt Enable Register, Section SFC_IDR56.5.4 SFC Interrupt Disable Register, Section SFC_IMR56.5.5 SFC Interrupt Mask Register and Section SFC_SR56.5.6 SFC Status Register.

Integrity Check Monitor (ICM)

Updated Section 57.5.4.2 Processing Period.

Advanced Encryption Standard (AES)

Section 59.1 Description: added XTS to supported modes.

Section 59.4.2 Operating Modes: added bullet for XTS mode; added bullet for CBC-MAC.

Last Output Data Mode: Added (CBC-MAC) to section title. Added details on CMAC algorithm.

Section59.4.8.1 Manual Mode: table "Authorized Input Data Registers": updated for XTS algorithm.

Section 59.4.8.3 DMA Mode: table "DMA Data Transfer Type for the Different Operating Modes": updated for XTS algorithm.

IPSEC Padding: added detail on padding length.

SSL Padding: added detail on incremental integer values.

Updated DMA Mode.

Updated If AES_MR.LOD = 1.

Triple Data Encryption Standard (TDES)

Last Output Data Mode (CBC-MAC): added “CBC-MAC” in section title and added second paragraph.

Updated Section 61.4.3.3 DMA Mode and Section 61.4.4.2.2 TDES_MR.LOD = 1.

Analog-to-Digital Controller (ADC)

ADC Channel Status Register: updated CHx bit description

Updated USCHx field description in ADC Channel Sequence 1 Register and ADC Channel Sequence 2 Register

Electrical Characteristics

In DC Characteristics updated:

- Vhyst parameter

- VDDIODDR

- conditions for VOL and VOH

Updated Section 66.3.2.2 Backup Mode with DDR in Self-Refresh.

Master Clock Waveform Parameters: changed VDDIODDR range.

Corrected references to CKGR_MOR bits and added VIL_XIN and VIH_XIN parameters in XIN Clock Electrical Characteristics.

Updated 12 MHz RC Oscillator Characteristics.

Updated PLLA Characteristics.

Added ADC Bias Current.

Added Pen Detect Characteristics.

Updated Analog Comparator Characteristics.

Two Wire Serial Bus Requirements: corrected definition of TWCK high and low periods.

DDR2-SDRAM System Clock Waveform Parameters: VDDIODDR range changed.

LPDDR1-SDRAM System Clock Waveform Parameters: VDDIODDR range changed.

Section 66.19 SSC Timings: added SSC14 and SSC15 timings

Schematic Checklist

ICE and JTAG: added note on JTAG boundary scan.

Errata

Removed from data sheet to create separate document, SAMA5D2 Family Silicon Errata and Data Sheet Clarification, document number DS80000803.

SAMA5D2 Series

70.7 Revision DS60001476C