54.7.1 PDMIC Control Register
Name: | PDMIC_CR |
Offset: | 0x00 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ENPDM | SWRST | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit 4 – ENPDM Enable PDM
Value | Description |
---|---|
0 | Disables the PDM and stops the conversions. |
1 | Enables the PDM and starts the conversions. |
Bit 0 – SWRST Software Reset
Warning: The read value of this bit is always 0.
Value | Description |
---|---|
0 | No effect. |
1 | Resets the PDMIC, simulating a hardware reset. |