39.6 GMAC Transmit Status Register

Name: GMAC_TSR
Offset: 0x014
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
        HRESP 
Access R/W 
Reset 0 
Bit 76543210 
   TXCOMPTFCTXGORLECOLUBR 
Access R/WR/WRR/WR/WR/W 
Reset 000000 

Bit 8 – HRESP System Bus Response

Set when the DMA block sees a system bus error. Writing a one clears this bit.

Bit 5 – TXCOMP Transmit Complete

Set when a frame has been transmitted. Writing a one clears this bit.

Bit 4 – TFC Transmit Frame Corruption Due to System Bus Error

Transmit frame corruption due to system bus error. Set if an error occurs while midway through reading transmit frame from the system bus, including system bus errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and GTXER asserted).

Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size.

Writing a one clears this bit.

Bit 3 – TXGO Transmit Go (Read only)

When high, transmit is active. When using the DMA interface, this bit represents the TXGO variable as specified in the transmit buffer description.

Bit 2 – RLE Retry Limit Exceeded

Writing a one clears this bit.

Bit 1 – COL Collision Occurred

Set by the assertion of collision. Writing a one clears this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision.

Bit 0 – UBR Used Bit Read

Set when a transmit buffer descriptor is read with its used bit set. Writing a one clears this bit.