35.7.9 MPDDRC Low-power DDR2 Low-power DDR3 Low-power Register
Name: | MPDDRC_LPDDR23_LPR |
Offset: | 0x28 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
DS[3:0] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
SEG_MASK[15:8] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
SEG_MASK[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
BK_MASK_PASR[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 27:24 – DS[3:0] Drive Strength
After the initialization sequence, as soon as the DS field is modified, Mode Register 3 is accessed automatically and DS bits are updated. Depending on the UPD_MR bit, update is done before entering Self-refresh mode or during a refresh command and a pending read or write access.
This field is unique to low-power DDR2-SDRAM and low-power DDR3-SDRAM. It selects the I/O drive strength as shown in the table below.
In case of low-power DDR2-SDRAM or low-power DDR3-SDRAM, the RDIV field in the MPDDRC_IO_CALIBR register must be set to same value of DS field.
Value | Name | Description |
---|---|---|
0 | – |
Reserved |
1 | DS_34_3 |
34.3 ohm typical |
2 | DS_40 |
40 ohm typical (default) |
3 | DS_48 |
48 ohm typical |
4 | DS_60 |
60 ohm typical |
5 | – |
Reserved |
6 | DS_80 |
80 ohm typical |
7 | DS_120 |
120 ohm typical |
8–15 | – |
Reserved |
Bits 23:8 – SEG_MASK[15:0] Segment Mask Bit
After the initialization sequence, as soon as the SEG_MASK field is modified, Mode Register 17 is accessed automatically and SEG_MASK bits are updated. Depending on the UPD_MR bit, update is done before entering Self-refresh mode or during a refresh command and a pending read or write access.
This mode is unique to the low-power DDR2-SDRAM-S4 and low-power DDR3-SDRAM devices. The number of Segment Mask bits differs with the density. For 1 Gbit density, 8 segments are used. In Self-refresh mode, when the Segment Mask bit is configured, the refresh operation is masked in the segment.
Value | Description |
---|---|
0 |
Segment is refreshed (= unmasked). |
1 |
Segment is not refreshed (= masked). |
Bits 7:0 – BK_MASK_PASR[7:0] Bank Mask Bit/PASR
Partial Array Self-Refresh (low-power DDR2-SDRAM-S4 devices and low-power DDR3-SDRAM only)
After the initialization sequence, as soon as the BK_MASK_PASR field is modified, Mode Register 16 is accessed automatically and BK_MASK_PASR bits are updated. Depending on the UPD_MR bit, update is done before entering Self-refresh mode or during a refresh command and a pending read or write access.
This mode is unique to the low-power DDR2-SDRAM-S4 and low-power DDR3-SDRAM devices. In Self-refresh mode, each bank of LPDDR2/LPDDR3 can be independently configured whether a self-refresh operation is taking place or not.
After the initialization sequence, as soon as the BK_MASK_PASR field is modified, the Extended Mode Register is accessed automatically and BK_MASK_PASR bits are updated. Depending on the UPD_MR bit, update is done before entering Self-refresh mode or during a refresh command and a pending read or write access.
Value | Description |
---|---|
0 |
Refresh is enabled (= unmasked). |
1 |
Refresh is disabled (= masked). |