The following configuration values are valid for all listed bit names
of this register:
0: Masked. This is the default value.
1: Enabled.
Name:
L2CC_IMR
Offset:
0x214
Reset:
0x00000000
Property:
Programmable in Auxiliary Control
register.
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
DECERR
Access
Reset
0
Bit
7
6
5
4
3
2
1
0
SLVERR
ERRRD
ERRRT
ERRWD
ERRWT
PARRD
PARRT
ECNTR
Access
Reset
0
0
0
0
0
0
0
0
Bit 8 – DECERR DECERR from L3 Memory
Bit 7 – SLVERR SLVERR from L3 Memory
Bit 6 – ERRRD Error on L2 Data RAM, Read
Bit 5 – ERRRT Error on L2 Tag RAM, Read
Bit 4 – ERRWD Error on L2 Data RAM, Write
Bit 3 – ERRWT Error on L2 Tag RAM, Write
Bit 2 – PARRD Parity Error on L2 Data RAM, Read
Bit 1 – PARRT Parity Error on L2 Tag RAM, Read
Bit 0 – ECNTR Event Counter 1/0 Overflow Increment
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