Jump to main content
Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, 500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB, PCI 5.0 Pre-Certified SAMA5D2 Series
Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, 500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB, PCI 5.0 Pre-Certified SAMA5D2 Series
Product Pages
ATSAMA5D21 ATSAMA5D22 ATSAMA5D23 ATSAMA5D24 ATSAMA5D26 ATSAMA5D27 ATSAMA5D28
  1. Home
  2. 46 Flexible Serial Communication Controller (FLEXCOM)
  3. 46.9 TWI Functional Description
  4. 46.9.6 TWI FIFOs
  5. 46.9.6.7 TWI Single Data Access
Previous | Next

SAMA5D2 Series

  • Introduction
  • Features
  • Description
  • 1 Configuration Summary
  • 2 Block Diagram
  • 3 Signal Description
  • 4 Microchip Recommended Power Management Solutions
  • 5 Safety and Security Features
  • 6 Package and Pinout
  • 7 Power Considerations
  • 8 Memories
  • 9 Event System
  • 10 System Controller
  • 11 Peripherals
  • 12 Chip Identifier (CHIPID)
  • 13 Cortex-A5 Processor (ARM)
  • 14 L2 Cache Controller (L2CC)
  • 15 Debug and Test Features
  • 16 Standard Boot Strategies
  • 17 CPU System Bus Matrix (CPUMX)
  • 18 Matrix (H64MX/H32MX)
  • 19 Special Function Registers (SFR)
  • 20 Special Function Registers Backup (SFRBU)
  • 21 Advanced Interrupt Controller (AIC)
  • 22 Watchdog Timer (WDT)
  • 23 Reset Controller (RSTC)
  • 24 Shutdown Controller (SHDWC)
  • 25 Periodic Interval Timer (PIT)
  • 26 Real-time Clock (RTC)
  • 27 System Controller Write Protection (SYSCWP)
  • 28 Slow Clock Controller (SCKC)
  • 29 Peripheral Touch Controller (PTC)
  • 30 Low Power Asynchronous Receiver (RXLP)
  • 31 Clock Generator
  • 32 Power Management Controller (PMC)
  • 33 Parallel Input/Output Controller (PIO)
  • 34 External Memories
  • 35 DDR-SDRAM Controller (MPDDRC)
  • 36 Static Memory Controller (SMC)
  • 37 DMA Controller (XDMAC)
  • 38 LCD Controller (LCDC)
  • 39 Ethernet MAC (GMAC)
  • 40 USB Device High Speed Port (UDPHS)
  • 41 USB Host High Speed Port (UHPHS)
  • 42 Audio Class D Amplifier (CLASSD)
  • 43 Inter-IC Sound Controller (I2SC)
  • 44 Synchronous Serial Controller (SSC)
  • 45 Two-wire Interface (TWIHS)
  • 46 Flexible Serial Communication Controller (FLEXCOM)
    • 46.1 Description
    • 46.2 Embedded Characteristics
    • 46.3 Block Diagram
    • 46.4 I/O Lines Description
    • 46.5 Product Dependencies
    • 46.6 Register Accesses
    • 46.7 USART Functional Description
    • 46.8 SPI Functional Description
    • 46.9 TWI Functional Description
      • 46.9.1 Transfer Format
      • 46.9.2 Modes of Operation
      • 46.9.3 Host Mode
      • 46.9.4 Multi-Host Mode
      • 46.9.5 Client Mode
      • 46.9.6 TWI FIFOs
        • 46.9.6.1 Overview
        • 46.9.6.2 Sending Data with FIFO Enabled
        • 46.9.6.3 Receiving Data with FIFO Enabled
        • 46.9.6.4 Sending/Receiving with FIFO Enabled in Client Mode
        • 46.9.6.5 Clearing/Flushing FIFOs
        • 46.9.6.6 TXRDY and RXRDY Behavior
        • 46.9.6.7 TWI Single Data Access
        • 46.9.6.8 TWI Multiple Data Access
        • 46.9.6.9 Transmit FIFO Lock
        • 46.9.6.10 FIFO Pointer Error
        • 46.9.6.11 FIFO Thresholds
        • 46.9.6.12 FIFO Flags
      • 46.9.7 TWI Comparison Function on Received Character
      • 46.9.8 TWI Register Write Protection
    • 46.10 Register Summary
  • 47 Universal Asynchronous Receiver Transmitter (UART)
  • 48 Serial Peripheral Interface (SPI)
  • 49 Quad Serial Peripheral Interface (QSPI)
  • 50 Secure Digital MultiMedia Card Controller (SDMMC)
  • 51 Image Sensor Controller (ISC)
  • 52 Controller Area Network (MCAN)
  • 53 Timer Counter (TC)
  • 54 Pulse Density Modulation Interface Controller (PDMIC)
  • 55 Pulse Width Modulation Controller (PWM)
  • 56 Secure Fuse Controller (SFC)
  • 57 Integrity Check Monitor (ICM)
  • 58 Advanced Encryption Standard Bridge (AESB)
  • 59 Advanced Encryption Standard (AES)
  • 60 Secure Hash Algorithm (SHA)
  • 61 Triple Data Encryption Standard (TDES)
  • 62 True Random Number Generator (TRNG)
  • 63 Analog Comparator Controller (ACC)
  • 64 Security Module (SECUMOD)
  • 65 Analog-to-Digital Controller (ADC)
  • 66 Electrical Characteristics
  • 67 Mechanical Characteristics
  • 68 Marking
  • 69 Ordering Information
  • 70 Revision History
  • Microchip Information

46.9.6.7 TWI Single Data Access

When FIFO is enabled and a byte access is performed in FLEX_TWI_THR, one byte is written in the FIFO. The same behavior applies for FLEX_TWI_RHR.

See TWI Transmit Holding Register and TWI Receive Holding Register.

However, it is possible to write/read multiple data each time FLEX_THR_THR/FLEX_US_RHR is accessed. See TWI Multiple Data Access.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

About

Company
Careers
Contact Us
Media Center
Investor Relations
Corporate Responsibility

Support

Microchip Forums
AVR Freaks
Design Help
Technical Support
Export Control Data
PCNs

Quick Links

microchipDIRECT.com
Microchip University
myMicrochip
Blogs
Reference Designs
Parametric Search
Microchip Logo

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, Arizona, USA

Microchip Facebook
Microchip LinkedIn
Microchip Twitter
Microchip Instagram
Microchip Weibo

© Copyright 1998-2024 Microchip Technology Inc. All rights reserved. Shanghai ICP Recordal No.09049794

Terms Of Use
Privacy Notice
Legal
Your Privacy Choices California Consumer Privacy Act (CCPA) Opt-Out Icon