32.20.1 Main System Bus Clock Switching Timings

The following tables give the worst case timings required for the Main System Bus clock to switch from one selected clock to another one. This is in the event that the prescaler is deactivated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added.

Table 32-2. Clock Switching Timings (Worst Case)
To From
Main Clock TD_SLCK PLL Clock
Main Clock 4 × TD_SLCK +
2.5 × Main Clock 3 × PLL Clock +

4 × TD_SLCK +
1 × Main Clock

TD_SLCK 0.5 × Main Clock + 
4.5 × TD_SLCK 3 × PLL Clock +
5 × TD_SLCK
PLL Clock 0.5 × Main Clock +
4 × TD_SLCK +
PLLCOUNT × TD_SLCK +
2.5 × PLL Clock 2.5 × PLL Clock +
5 × TD_SLCK +
PLLCOUNT × TD_SLCK 2.5 × PLL Clock +
4 × TD_SLCK +
PLLCOUNT × TD_SLCK
Note: PLL designates either the PLLA or the UPLL Clock. PLLCOUNT designates either PLLACOUNT or UPLLCOUNT.
Table 32-3. Clock Switching Timings Between Two PLLs (Worst Case)
To From
PLLA Clock UPLL Clock
PLLA Clock 2.5 × PLLA Clock +
4 × TD_SLCK +
PLLACOUNT × TD_SLCK 3 × PLLA Clock +
4 × TD_SLCK +
1.5 × PLLA Clock
UPLL Clock 3 × UPLL Clock +
4 × TD_SLCK +
1.5 × UPLL Clock 2.5 × UPLL Clock +
4 × TD_SLCK +
UPLLCOUNT × TD_SLCK