18.13.15 Security Peripheral Select x Registers

This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.

The actual number of peripherals implemented is device-specific; refer to the “Peripheral Identifiers” section for details.

Each MATRIX_SPSELR can configure the access security type for up to 32 peripherals:
  • MATRIX_SPSELR1 configures the access security type for peripheral identifiers 0–31 (bits NSECP0–NSECP31).
  • MATRIX_SPSELR2 configures the access security type for peripheral identifiers 32–63 (bits NSECP0–NSECP31).
  • MATRIX_SPSELR3 configures the access security type for peripheral identifiers 64–95 (bits NSECP0–NSECP31).
Reset values are as follows:
  • MATRIX_SPSELR1: 0x000D2504 for H32MX, 0xFFF2DAFB for H64MX
  • MATRIX_SPSELR2: 0x011C0000 for H32MX, 0xFFE7FFFF for H64MX
  • MATRIX_SPSELR3: 0xFFFFFFFA for H32MX, 0xFFFFFFE7 for H64MX
Name: MATRIX_SPSELRx
Offset: 0x02C0 + (x-1)*0x04 [x=1..3]
Property: Read/Write

Bit 3130292827262524 
 NSECP31NSECP30NSECP29NSECP28NSECP27NSECP26NSECP25NSECP24 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset  
Bit 2322212019181716 
 NSECP23NSECP22NSECP21NSECP20NSECP19NSECP18NSECP17NSECP16 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset  
Bit 15141312111098 
 NSECP15NSECP14NSECP13NSECP12NSECP11NSECP10NSECP9NSECP8 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset  
Bit 76543210 
 NSECP7NSECP6NSECP5NSECP4NSECP3NSECP2NSECP1NSECP0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – NSECPy Non-secured Peripheral

ValueDescription
0

The selected peripheral address space is configured as “Secured” access (value of ‘0’ has no effect if the peripheral security type is “Peripheral Always Non-secured”).

1

The selected peripheral address space is configured as “Non-secured” access (value of ‘1’ has no effect if the peripheral security type is “Peripheral Always Secured”).