65.7.7 ADC Channel Status Register

Name: ADC_CHSR
Offset: 0x18
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     CH11CH10CH9CH8 
Access WWWW 
Reset 0000 
Bit 76543210 
 CH7CH6CH5CH4CH3CH2CH1CH0 
Access WWWWWWWW 
Reset 00000000 

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – CHx Channel x Status

ValueDescription
0 The corresponding channel (or part of sequence, see ADC_SEQyR.USCHx field) is disabled.
1 The corresponding channel (or part of sequence, see ADC_SEQyR.USCHx field) is enabled. As an example, when ADC_MR.USEQ=1 and ADC_CHSR.CH2=1, the channel configured in ADC_SEQ1R.USCH3 is part of the sequence of conversions.