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Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, 500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB, PCI 5.0 Pre-Certified SAMA5D2 Series
Introduction
Features
Description
1 Configuration Summary
2 Block Diagram
3 Signal Description
4 Microchip Recommended Power Management Solutions
4.1 MCP16502 PMIC
4.2 MCP16501 PMIC
5 Safety and Security Features
5.1 Design for Safety and IEC60730 Class B Certification
5.2 Design for Security
5.3 Safety and IEC 60730 Features
5.4 Security Features
6 Package and Pinout
6.1 Packages
6.2 Pinouts
7 Power Considerations
7.1 Power Supplies
7.2 Power-up Considerations
7.3 Power-down Considerations
7.4 Power Supply Sequencing at Backup Mode Entry and Exit
8 Memories
8.1 Embedded Memories
8.2 External Memory
9 Event System
9.1 Real-time Event List
9.2 Real-time Event Mapping
10 System Controller
10.1 Power-On Reset
11 Peripherals
11.1 Peripheral Mapping
11.2 Peripheral Identifiers
11.3 Peripheral Signal Multiplexing on I/O Lines
11.4 Peripheral Clock Types
12 Chip Identifier (CHIPID)
12.1 Description
12.2 Embedded Characteristics
12.3 Register Summary
13 Cortex-A5 Processor (ARM)
13.1 Reference Documents
13.2 Description
13.3 Embedded Characteristics
13.4 Block Diagram
13.5 Programmer Model
13.6 Memory Management Unit (MMU)
14 L2 Cache Controller (L2CC)
14.1 Description
14.2 Embedded Characteristics
14.3 Product Dependencies
14.4 Functional Description
14.5 Register Summary
15 Debug and Test Features
15.1 Description
15.2 Embedded Characteristics
15.3 Debug and Test Block Diagrams
15.4 Application Examples
15.5 Debug and Test Pin Description
15.6 Functional Description
15.7 Boundary JTAG ID Register
Boundary JTAG ID Register
15.8 Cortex-A5 DP Identification Code Register IDCODE
16 Standard Boot Strategies
16.1 Description
16.2 Chip Access Using JTAG Connection
16.3 Flow Diagram
16.4 Chip Setup
16.5 Boot Configuration
16.6 SAM-BA Monitor
16.7 Fuse Box Controller
17 CPU System Bus Matrix (CPUMX)
17.1 Description
17.2 Embedded Characteristics
17.3 Block Diagram
17.4 Operation
17.5 Register Summary
18 Matrix (H64MX/H32MX)
18.1 Description
18.2 Embedded Characteristics
18.3 64-bit Matrix (H64MX)
18.4 32-bit Matrix (H32MX)
18.5 Memory Mapping
18.6 Special Bus Granting Mechanism
18.7 No Default Host
18.8 Last Access Host
18.9 Fixed Default Host
18.10 Arbitration
18.11 Register Write Protection
18.12 TrustZone Technology
18.13 Register Summary
19 Special Function Registers (SFR)
19.1 Description
19.2 Embedded Characteristics
19.3 Register Summary
20 Special Function Registers Backup (SFRBU)
20.1 Description
20.2 Embedded Characteristics
20.3 Register Summary
21 Advanced Interrupt Controller (AIC)
21.1 Description
21.2 Embedded Characteristics
21.3 Block Diagram
21.4 Application Block Diagram
21.5 Detailed Block Diagram
21.6 I/O Line Description
21.7 Product Dependencies
21.8 Functional Description
21.9 Register Summary
22 Watchdog Timer (WDT)
22.1 Description
22.2 Embedded Characteristics
22.3 Block Diagram
22.4 Functional Description
22.5 Register Summary
23 Reset Controller (RSTC)
23.1 Description
23.2 Embedded Characteristics
23.3 Block Diagram
23.4 Functional Description
23.5 Register Summary
24 Shutdown Controller (SHDWC)
24.1 Description
24.2 Embedded Characteristics
24.3 Block Diagram
24.4 I/O Lines Description
24.5 Product Dependencies
24.6 Functional Description
24.7 Register Summary
25 Periodic Interval Timer (PIT)
25.1 Description
25.2 Embedded Characteristics
25.3 Block Diagram
25.4 Functional Description
25.5 Register Summary
26 Real-time Clock (RTC)
26.1 Description
26.2 Embedded Characteristics
26.3 Block Diagram
26.4 Product Dependencies
26.5 Functional Description
26.6 Register Summary
27 System Controller Write Protection (SYSCWP)
27.1 Functional Description
27.2 Register Summary
28 Slow Clock Controller (SCKC)
28.1 Description
28.2 Embedded Characteristics
28.3 Block Diagram
28.4 Functional Description
28.5 Register Summary
29 Peripheral Touch Controller (PTC)
29.1 Description
29.2 Embedded Characteristics
29.3 Block Diagram
29.4 Signal Description
29.5 Product Dependencies
29.6 Functional Description
29.7 Register Summary
30 Low Power Asynchronous Receiver (RXLP)
30.1 Description
30.2 Embedded Characteristics
30.3 Block Diagram
30.4 Product Dependencies
30.5 Functional Description
30.6 Register Summary
31 Clock Generator
31.1 Description
31.2 Embedded Characteristics
31.3 Block Diagram
31.4 Slow Clock
31.5 Main Clock
31.6 Divider and PLLA Block
31.7 UTMI PLL Clock
31.8 Audio PLL
32 Power Management Controller (PMC)
32.1 Description
32.2 Embedded Characteristics
32.3 Block Diagram
32.4 Main System Bus Clock Controller
32.5 Processor Clock Controller
32.6 Matrix Clock Controller
32.7 Programmable Clock Controller
32.8 Core and Bus Independent Clocks for Peripherals
32.9 Peripheral and Generic Clock Controller
32.10 LCDC Clock Controller
32.11 ISC Clock Controller
32.12 USB Device and Host Clocks
32.13 DDR2/LPDDR/LPDDR2 Clock Controller
32.14 Fast Start-up from Ultra-Low-Power 0 (ULP0) Mode
32.15 Fast Start-up from Ultra-Low-Power 1 (ULP1) Mode
32.16 Asynchronous Partial Wake-up
32.17 Main Crystal Oscillator Failure Detection
32.18 32.768 kHz Crystal Oscillator Frequency Monitor
32.19 Programming Sequence
32.20 Clock Switching Details
32.21 Register Write Protection
32.22 Register Summary
33 Parallel Input/Output Controller (PIO)
33.1 Description
33.2 Embedded Characteristics
33.3 Block Diagram
33.4 Product Dependencies
33.5 Functional Description
33.6 I/O Lines Programming Example
33.7 Register Summary
34 External Memories
34.1 Multiport DDR-SDRAM Controller (MPDDRC)
34.2 External Bus Interface (EBI)
35 DDR-SDRAM Controller (MPDDRC)
35.1 Description
35.2 Embedded Characteristics
35.3 Block Diagram
35.4 Product Dependencies, Initialization Sequence
35.5 Functional Description
35.6 Software Interface/SDRAM Organization, Address Mapping
35.7 Register Summary
36 Static Memory Controller (SMC)
36.1 Description
36.2 Embedded Characteristics
36.3 Block Diagram
36.4 I/O Lines Description
36.5 Multiplexed Signals
36.6 Application Example
36.7 Product Dependencies
36.8 External Memory Mapping
36.9 Connection to External Devices
36.10 Standard Read and Write Protocols
36.11 Scrambling/Unscrambling Function
36.12 Automatic Wait States
36.13 Data Float Wait States
36.14 External Wait
36.15 Slow Clock Mode
36.16 Register Write Protection
36.17 NFC Operations
36.18 PMECC Controller Functional Description
36.19 Software Implementation
36.20 Register Summary
37 DMA Controller (XDMAC)
37.1 Description
37.2 Embedded Characteristics
37.3 Block Diagram
37.4 DMA Controller Peripheral Connections
37.5 Functional Description
37.6 Linked List Descriptor Operation
37.7 XDMAC Maintenance Software Operations
37.8 XDMAC Software Requirements
37.9 Register Summary
38 LCD Controller (LCDC)
38.1 Description
38.2 Embedded Characteristics
38.3 Block Diagram
38.4 I/O Lines Description
38.5 Product Dependencies
38.6 Functional Description
38.7 Register Summary
39 Ethernet MAC (GMAC)
39.1 Description
39.2 Embedded Characteristics
39.3 Block Diagram
39.4 Signal Interfaces
39.5 Product Dependencies
39.6 Functional Description
39.7 Programming Interface
39 Register Summary
40 USB Device High Speed Port (UDPHS)
40.1 Description
40.2 Embedded Characteristics
40.3 Block Diagram
40.4 Typical Connection
40.5 Product Dependencies
40.6 Functional Description
40 Register Summary
41 USB Host High Speed Port (UHPHS)
41.1 Description
41.2 Embedded Characteristics
41.3 Block Diagram
41.4 Typical Connection
41.5 Product Dependencies
41.6 Functional Description
41 Register Summary
42 Audio Class D Amplifier (CLASSD)
42.1 Description
42.2 Embedded Characteristics
42.3 Block Diagram
42.4 Pin Name List
42.5 Product Dependencies
42.6 Functional Description
42.7 Register Summary
43 Inter-IC Sound Controller (I2SC)
43.1 Description
43.2 Embedded Characteristics
43.3 Block Diagram
43.4 I/O Lines Description
43.5 Product Dependencies
43.6 Functional Description
43.7 I2SC Application Examples
43.8 Register Summary
44 Synchronous Serial Controller (SSC)
44.1 Description
44.2 Embedded Characteristics
44.3 Block Diagram
44.4 Application Block Diagram
44.5 SSC Application Examples
44.6 Pin Name List
44.7 Product Dependencies
44.8 Functional Description
44.9 Register Summary
45 Two-wire Interface (TWIHS)
45.1 Description
45.2 Embedded Characteristics
45.3 List of Abbreviations
45.4 Block Diagram
45.5 Product Dependencies
45.6 Functional Description
45.7 Register Summary
46 Flexible Serial Communication Controller (FLEXCOM)
46.1 Description
46.2 Embedded Characteristics
46.3 Block Diagram
46.4 I/O Lines Description
46.5 Product Dependencies
46.6 Register Accesses
46.7 USART Functional Description
46.8 SPI Functional Description
46.9 TWI Functional Description
46.10 Register Summary
47 Universal Asynchronous Receiver Transmitter (UART)
47.1 Description
47.2 Embedded Characteristics
47.3 Block Diagram
47.4 Product Dependencies
47.5 Functional Description
47.6 Register Summary
48 Serial Peripheral Interface (SPI)
48.1 Description
48.2 Embedded Characteristics
48.3 Block Diagram
48.4 Application Block Diagram
48.5 Signal Description
48.6 Product Dependencies
48.7 Functional Description
48.8 Register Summary
49 Quad Serial Peripheral Interface (QSPI)
49.1 Description
49.2 Embedded Characteristics
49.3 Block Diagram
49.4 Signal Description
49.5 Product Dependencies
49.6 Functional Description
49.7 Register Summary
50 Secure Digital MultiMedia Card Controller (SDMMC)
50.1 Description
50.2 Embedded Characteristics
50.3 Reference Documents
50.4 Block Diagram
50.5 Application Block Diagram
50.6 Pin Name List
50.7 Product Dependencies
50.8 SD/SDIO Operating Mode
50.9 e.MMC Operating Mode
50.10 SDR104 / HS200 Tuning
50.11 I/O Calibration
50.12 Register Summary
51 Image Sensor Controller (ISC)
51.1 Description
51.2 Embedded Characteristics
51.3 ISC Block Diagram and Use Cases
51.4 I/O Lines Description
51.5 Product Dependencies
51.6 Functional Description
51.7 Register Summary
52 Controller Area Network (MCAN)
52.1 Description
52.2 Embedded Characteristics
52.3 Block Diagram
52.4 Product Dependencies
52.5 Functional Description
52.6 Register Summary
53 Timer Counter (TC)
53.1 Description
53.2 Embedded Characteristics
53.3 Block Diagram
53.4 Pin List
53.5 Product Dependencies
53.6 Functional Description
53.7 Register Summary
54 Pulse Density Modulation Interface Controller (PDMIC)
54.1 Description
54.2 Embedded Characteristics
54.3 Block Diagram
54.4 Signal Description
54.5 Product Dependencies
54.6 Functional Description
54.7 Register Summary
55 Pulse Width Modulation Controller (PWM)
55.1 Description
55.2 Embedded Characteristics
55.3 Block Diagram
55.4 I/O Lines Description
55.5 Product Dependencies
55.6 Functional Description
55.7 Register Summary
56 Secure Fuse Controller (SFC)
56.1 Description
56.2 Embedded Characteristics
56.3 Block Diagram
56.4 Functional Description
56.5 Register Summary
57 Integrity Check Monitor (ICM)
57.1 Description
57.2 Embedded Characteristics
57.3 Block Diagram
57.4 Product Dependencies
57.5 Functional Description
57.6 Register Summary
58 Advanced Encryption Standard Bridge (AESB)
58.1 Description
58.2 Embedded Characteristics
58.3 Product Dependencies
58.4 Functional Description
58.5 Register Summary
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59 Advanced Encryption Standard (AES)
59.1 Description
59.2 Embedded Characteristics
59.3 Product Dependencies
59.4 Functional Description
59.5 Register Summary
60 Secure Hash Algorithm (SHA)
60.1 Description
60.2 Embedded Characteristics
60.3 Product Dependencies
60.4 Functional Description
60.5 Register Summary
61 Triple Data Encryption Standard (TDES)
61.1 Description
61.2 Embedded Characteristics
61.3 Product Dependencies
61.4 Functional Description
61.5 Register Summary
62 True Random Number Generator (TRNG)
62.1 Description
62.2 Embedded Characteristics
62.3 Block Diagram
62.4 Product Dependencies
62.5 Functional Description
62.6 Register Summary
63 Analog Comparator Controller (ACC)
63.1 Description
63.2 Embedded Characteristics
63.3 Block Diagram
63.4 Signal Description
63.5 Product Dependencies
63.6 Functional Description
63.7 Register Summary
64 Security Module (SECUMOD)
64.1 Description
64.2 Embedded Characteristics
64.3 Block Diagram
64.4 Product Dependencies
64.5 Functional Description
64.6 Register Summary
65 Analog-to-Digital Controller (ADC)
65.1 Description
65.2 Embedded Characteristics
65.3 Block Diagram
65.4 Signal Description
65.5 Product Dependencies
65.6 Functional Description
65.7 Register Summary
66 Electrical Characteristics
66.1 Absolute Maximum Ratings
66.2 DC Characteristics
66.3 Power Consumption
66.4 Clock Characteristics
66.5 Oscillator Characteristics
66.6 PLL Characteristics
66.7 USB HS Characteristics
66.8 PTC Characteristics
66.9 ADC Characteristics
66.10 Analog Comparator Characteristics
66.11 POR Characteristics
66.12 SMC Timings
66.13 FLEXCOM Timings
66.14 USART in Asynchronous Modes
66.15 SPI Timings
66.16 TWI Timings
66.17 QSPI Timings
66.18 MPDDRC Timings
66.19 SSC Timings
66.20 PDMIC Timings
66.21 I2SC Timings
66.22 ISC Timings
66.23 SDMMC Timings
66.24 GMAC Timings
67 Mechanical Characteristics
67.1 289-Ball Low Profile Fine Pitch Ball Grid Array (AMB) - 14x14x1.4 mm Body [LFBGA] Atmel Legacy Global Package Code CCZ
67.2 256-Ball Thin Fine Pitch Ball Grid Array (AYB) - 8x8x1.05 mm Body [TFBGA]
67.3 196-Ball Thin Fine Pitch Ball Grid Array (BAB) - 11x11 mm Body [TFBGA]
68 Marking
69 Ordering Information
70 Revision History
70.1 Revision DS60001476J - 11/2022
70.2 Revision DS60001476H - 03/2022
70.3 Revision DS60001476G - 03/2021
70.4 Revision DS60001476F - 09/2020
70.5 Revision DS60001476E - 09/2020
70.6 Revision DS60001476D - 02/2020
70.7 Revision DS60001476C
70.8 Revision DS60001476B
70.9 Revision DS60001476A
70.10 Revision 11267E
70.11 Revision 11267D
70.12 Revision 11267C
70.13 Revision 11267B
70.14 Revision 11267A
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